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Digital Verification
Job Description:
Creating test plan according to design spec.
Designing and developing verification environment
Creating UVM test cases
Creating code and function coverage report.
Requirement:
1. Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC design or verification.
2. Familiar with Verilog and RTL design
3. Familiar with System-Verilog and UVM verification methodology
4. Familiar with script languages(perl,tcl,sh etc.) is a plus
5. Good problem solving and communication skills |
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