芯原微电子(上海)2019校招（内部推荐）

SpunkyGG

芯原微电子是一家芯片设计平台即服务（Silicon Platform as a Service，SiPaaS）提供商，为包含移动互联设备、数据中心、物联网、汽车、工业和医疗设备在内的广泛终端市场提供全面的系统级芯片（Soc）和系统级封装（SiP）解决方案。
目前公司发展不错。需求的岗位种类众多，包括ASIC 设计，验证，DFT，测试。GPU，视频，AR/AI研发，嵌入式，软件等。都在上海。
岗位和具体要求如下，有兴趣的同学可以联系我：2420747162@qq.com


芯片系统设计/验证工程师
SoC Design/Verification Engineer
职位描述：
 独立完成ASIC功能模块的设计/验证任务，包括：需求分析，架构定义，RTL编码，模块设计及验证，系统集成及验证，逻辑综合和时序分析
 密切配合系统工程师、物理实现工程师和测试工程师，解决功能验证、平面布置图设计、时序优化/关闭和测试方面的问题
职位要求：
 硕士及以上学历，电子工程或计算机科学相关专业
 有相关ASIC设计/验证工作（包括课程项目）经验
 熟练应用EDA工具（Synopsys或Cadence）或熟悉RTL Coding/Verilog/UVM/SystemVerilog者优先
 富有事业心和团队合作精神，沟通表达能力良好
工作地点：
 上海
Responsibilities:
 Capable of independently contributing to and working on the design/verification of ASIC function blocks in terms of Design Spec, Architecture definition, RTL coding, block design/verification, system integration/verification; logic synthesize and timing analyze (STA)
 Work closely with system engineers, physical implementation designers, and testing engineers to solve functional verification, floorplan design, timing optimization/closure and testing consideration
 Be responsible for micro-architecture design, RTL design, block-/chip-level verification, as a bridge to ASIC physical implementation
Requirements:
 Master/PhD degree in EE/CS related specialties
 At least 1+ years of working experience in ASIC design/verification, including course projects
 Possessing the independent mastery of EDA tools(Synopsys or Cadence) and capability of solving technical issues as below are a must: Design specification, RTL coding and style critique, block design, chip-level integration; logic synthesize and timing analyze (STA); System C modeling, System Verilog based on VMM/OVM methodology
 Solid knowledge and proven track record in design flow and methodologies for deep submicron ASIC development is a plus
 Strong understanding of ASIC design issues and deep considerations relating to silicon success
 Self motivated, team work, and good communication are a must
Location:
 Shanghai
射频电路设计工程师
RF Circuit Design Engineer
职位描述：
 设计开发CMOS 深亚微米模拟射频电路
 指导、监督版图设计
 协助设计测试板, 调试验证测试芯片
职位要求：
 硕士及以上学历，电子工程相关专业
 相关课程知识及项目经验
 有LNA,MIXER,TIA,VCO,PLL,LPF&VGA,PA或其他RF相关电路单项或多项设计经验者优先
 富有事业心和团队合作精神，沟通表达能力良好
工作地点：
 上海
Responsibilities:
 Devise and develop deep sub-micron CMOS analog RF circuit
 Guide and/or supervise layout design
 Assist in the design of test boards, debug and verify test chips
Requirements:
 MS/PHD degree, majored in EE
 Course knowledge and project experience in the related areas
 Have experience in one or some of the following disciplines: LNA,MIXER,TIA,VCO,PLL,LPF&VGA,PA, or other RF blocks
 Self motivated, good communication and team work skills are a must
Location:
 Shanghai
设计实现工程师
Design Implementation Engineer
职位描述：
 掌握并熟练应用从RTL到GDS的设计流程
 完成时序约束,逻辑综合,静态时序分析,测试用逻辑电路的设计
 完成布图布线,物理验证
 为客户/现场应用工程师/销售人员提供技术支持
职位要求：
 硕士及以上学历，电子工程相关专业
 具备以下单项或多项经验者优先: RTL到GDS的设计实现；芯片级测试；ASIC编码和模拟；ASIC物理版图；集成电路制造和工艺
 富有事业心和团队合作精神,沟通表达能力良好，中英文流利
工作地点：
 上海
Responsibilities:
 Master and be familiar with the RTL to GDS design flow
 Complete timing constraint, logic synthesis, STA, test logic circuit design
 Complete P&R, physical verification
 Provide technical support for customer/FAE/sales
Requirements:
 Master of EE or above
 Study hard and work actively
 Have following single or multiple experiences: design implementation from RTL to GDS, chip level testing, ASIC coding and simulation, ASIC physical layout, IC manufacture and process
 Full of enterprise and the spirit of teamwork, good ability to communicate and express, fluent in Mandarin and English
Location:
 Shanghai
DFT(可测性设计)工程师
DFT(Design for Test) Engineer
职位描述：
 完成DFT逻辑设计,包括:存储器内建自测试,存储器内建自修复,扫描链插入,边界扫描链插入,宏测试
 完成DFT模式时序约束,帮助DFT模式时序收敛
 帮助芯片bring-up,完成测试向量的调试,良率的提升
 为客户/现场应用工程师/销售人员提供技术支持
职位要求：
 硕士及以上学历，电子工程相关专业
 具备以下单项或多项经验者优先: 芯片级测试；ASIC编码和模拟；RTL到GDS的设计实现
 富有事业心和团队合作精神,沟通表达能力良好,中英文流利
工作地点：
 上海
Responsibilities:
 Complete DFT logic design, including: memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing
 Complete DFT mode timing constraint, support DFT mode timing closure
 Support chip bring-up, complete test pattern debugging, yield improvement
 Provide technical support for customer/FAE/sales
Requirements:
 Master of EE or above
 Study hard and work actively
 Have following single or multiple experiences: chip level testing, ASIC coding and simulation, design implementation from RTL to GDS
 Full of enterprise and the spirit of teamwork, good ability to communicate and express, fluent in Mandarin and English
Location:
 Shanghai
基础IP电路设计工程师
Foundation IP Circuit Design Engineer
职位描述：
 设计基础IP, 包括基本单元库, 各类存储器,及定制最优化PPA等
 指导版图工程师, 以保证最优的后仿结果
 为设计的基础IP建模, 包括Verilog, Synopsys liberty模型等,以支持主流EDA设计工具
 为测试芯片设计测试电路, 辅助测试工作
职位要求：
 硕士及以上学历，电子工程相关专业
 了解器件物理, 熟悉常用编程语言和主流EDA工具
 富有事业心和团队合作精神, 积极主动,沟通表达能力良好
工作地点：
 上海
Responsibilities:
 Design and develop deep sub-micron foundation IP circuits including standard cells, memory and customization cells for chip PPA optimization
 Guide layout designer, assist in layout optimization based on post-layout simulation results
 Characterize and generate design models supporting major EDA design flows including Verilog, Synopsys liberty model etc.
 Design test chip testing circuits for STD/MEM/IO libraries and assist in testing.
Qualifications:
 MS degree or higher in EE or related major.
 Strong background on device physics. Familiar and hands-on experience in script language and behavior model, ie,Tcl, Perl, Verilog, etc. Experiences on Cadence/Synopsys/Mentor's EDA tools
 Self motivated, good communication skill and team work spirit are a must.
Location：
 Shanghai
模拟电路设计工程师
Analog Circuit Design Engineer
职位描述：
 设计开发CMOS 深亚微米模拟电路
 指导、监督版图设计
 协助设计测试板, 调试验证测试芯片
职位要求：
 硕士及以上学历，电子工程相关专业
 有相关课程知识及项目经验
 有以下单项或多项设计经验者优先：VCO, PLL, DLL, PCIex, USB, SATA, LVDS, HDMI, display port, DDR PHY, high-speed SAR ADC , etc
 富有事业心和团队合作精神，沟通表达能力良好
工作地点：
 上海
Responsibilities:
 Devise and develop deep sub-micron CMOS analog circuit
 Guide and/or supervise layout
 Assist in the design of test boards so as to debug and verify test chips
Requirements:
 MS degree, majored in EE
 Course knowledge and project experience in the related areas
 Have experience on one or some of the following disciplines: VCO, PLL, DLL, PCIex, USB, SATA, LVDS, HDMI, display port, DDR PHY, high-speed SAR ADC, etc
 Self motivated, good communication and team work skills are a must
Location:
 Shanghai
系统应用工程师
System Application Engineer
职位描述：
 IC和SoC设计中的IP/子系统/系统级的FPGA验证
 设计及开发ASIC/SoC项目中的嵌入式系统，包括设计和调试板级硬件和固件
 内部测试IC和SoC产品；确定系统的要求，设计原型以及指导客户正确应用产品
 为客户/现场应用工程师/销售人员提供技术支持
职位要求：
 本科及以上学历，电子、计算机或自动化相关专业
 有FPGA综合实现和调试经验者优先
 良好的C / C++基础，熟悉ARM, Power PC, ZSP/MIPS的芯片系统架构和外围系统
 有较强的沟通能力，学习能力和问题解决能力以及团队合作精神
工作地点：
 上海
Responsibilities:
 Carry out System/Sub-system/IP FPGA verification/validation for IC and SoC designs
 Perform in-house validation for IC and SoC products
 Design and develop Embedded System in ASIC/SoC projects, including design and debug hardware and firmware
 Work with project members to determine system requirement, design prototyping and support customers in product applications
 Play an important role in SoC and System project development
 Provide technical support for Customer/FAE/Sales
Requirements:
 Bachelor degree or above in EE, CS or Automation
 Good knowledge/experience of FPGA synthesis, implement and debug
 Good knowledge/experience in C/C++ and ASM
 Good experience in debugging board, firmware and FPGA, etc on system level
 Good architecture knowledge about at least 1 type of the following SoC systems: ARM, Power PC, ZSP or MIPS and peripheral systems
 Clear understanding of hardware/software interaction and system level tradeoffs
 Good problem solving and design documentation skill, self motivated, good communication skill and team work spirits
Location:
 Shanghai
嵌入式软件工程师
Embedded Software Engineer
职位描述：
 开发和移植ASIC/SoC项目中的嵌入式软件，包括bootloader, Linux/Android应用程序等
 开发软件以验证SoC系统/子系统/IP；确定系统的要求，设计原型以及指导客户正确应用产品
 为客户/现场应用工程师/销售人员提供技术支持
职位要求：
 本科及以上学历，电子、计算机或自动化相关专业
 有嵌入式系统（BSP、设备驱动程序和API）开发经验者优先；熟悉至少一种SoC系统的架构：ARM/MIPS/Power PC
 熟悉C/C++，深入理解操作体系原理尤其是Linux kernel者优先
 有较强的沟通能力，学习能力和问题解决能力以及团队合作精神
工作地点：
 上海
Responsibilities:
 Design and develop embedded software in ASIC/SoC projects, including design and debug bootloader, Linux kernel, Android application, etc.
 Develop software for System/Sub-system/IP FPGA verification/validation
 Work with project members to determine system requirement, design prototyping and support customers in product applications
 Play an important role in SoC and System project development
 Provide technical support for Customer/FAE/Sales
Requirements:
 Bachelor degree or above in EE, CS or Automation
 Good architecture knowledge about at least 1 type of the following SoC systems: ARM/MIPS/Power PC
 Good knowledge/experience in embedded system development, including BSP, Device Driver and API development
 Clear understanding of hardware/software interaction and system level tradeoffs
 Knowledge about hardware
 Good knowledge/experience in C/C++, OS, especially Linux kernel
 Good problem solving and design documentation skill, self motivated, good communication skill and team work spirits
Location:
 Shanghai
集成电路设计/验证工程师
ASIC Design/Verification Engineer
职位描述：
 独立完成人工智能/深度学习/视频编解码/语音及音频编解码/图像传感器/GPU等 IP的设计或者验证任务，包括模块的规格定义，模块架构及微架构设计，RTL编码，仿真和综合
职位要求：
 硕士及以上学历，计算机科学或电子工程相关专业
 有相关集成电路设计/验证工作（包括课程项目）经验
 有人工智能，深度学习，视频编解码或图形图像处理模块设计经验者优先
 富有事业心和团队合作精神，沟通表达能力良好，中英文沟通流利
工作地点：
 上海
Responsibilities:
 Develop or Verification AI, Deep learning, VPU，ZSP，ISP or GPU IP modules including module spec definition, architecture and micro architecture design, RTL coding, simulation and synthesis
Requirements:
 Master degree or above in CS/EE
 At least 1+ years of working experience in ASIC design/verification(including course projects)
 Familiar with all aspects of the frontend ASIC design flow including RTL design, verification, synthesis, and timing analysis, DFT, etc.
 Experience in AI, deep learning, VPU or graphic, image process is a big plus
 Good written and spoken English
 Good communication skills and able to work both independently and in a team
Location：
 Shanghai
软件工程师
Software Engineer
职位描述：
 参与IP设计的软件开发，包括图形处理器，视频编解码，音频数字信息处理，图像传感器和深度学习加速器相关的软件开发项目
 从底层的驱动到上层中间件及应用层开发，完成性能分析调试
 和硬件部门共同完成IP的设计，开发和验证测试以及和支持客户完成集成和量产工作
职位要求：
 本科及以上学历，电子、计算机或自动化相关专业
 熟悉C语言，有良好的编程习惯；了解操作系统概念和基本的数据结构算法
 阅读和掌握大规模软件库知识者优先
 富有事业心和团队合作精神，沟通表达能力良好
工作地点：
 上海
Responsibilities:
As a software engineer, you will work on software development projects for GPU, VPU, ZSP, ISP and Machine Learning accelerator from low level driver to middleware and application and performance analysis. You will also work with hardware design team together to verify and test the IP. Helping out customers to integrate our IPs and support their production is also one of the responsibilities.
Requirements:
 Good C programming skill.
 Understand basic concepts in operation system and data structure/algorithm.
 Experience with large software code bases is a plus.
 Experience in any projects related is a plus.
 Good written and spoken English
 Good communication skills and team player.
Location：
 Shanghai

黑崎一护776

您好，我想请问一下，芯原开始发校招offer了吗？我6号面过了还和老板握手了。。。。还会不会被刷呢？

qwer2016

还在招吗？

happily0221

顶起来。。。。。。