Sr. Digital Verification
Engineer-上海 杭州 成都 深圳
Job
Description： Creating test plan according to design spec. Designing and developing verification environment Creating UVM test cases Creating code and function coverage report.
Requirement:
1. Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC design or verification.
2. Familiar with Verilog and RTL design
3. Familiar with System-Verilog and UVM verification methodology
4. Familiar with script languages(perl,tcl,sh etc.) is a plus
5. Familiar with digital signal processing knowledge is a plus
6. Good problem solving and communication skills
微信账号：473421885
有意者简历可发：473421885@qq.com | 
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发表于 2018-9-3 15:43:16
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