【AMD】MTS Verification Engineer (Cache Sub-System)

RecruiterAMD

We're hiring !! If you have interest, pls. send your resume to nina.zhang@amd.com (Work location: Haidian District, Beijing)

Job description:
We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead Graphics Cache Sub-System function verification domains including:
1.  Graphics Cache Sub-System DV testbench and infrastructure development and maintenance
2.  Create and execute Cache Sub-System testplan.
3.  Implement directed and random test cases in C++/SV/UVM, as well as checkers and assertions
4.  Support integration and qualification of SOC integration.
5.  Help to improve DV environment building flow

Requirement:
-   DV lead experience is a must
-   Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both
-   Knowledgeable in C++ & SV/UVM development, familiar with scripting languages like Ruby/Perl/Makefile…
-   Strong problem solving and communication skills
-   Knowledge on computer architecture and Cache system is highly preferred
-   Experience in power-aware verification is an asset