Cadence急招崗位 数字后端芯片设计、数字前端验证AE（SH / BJ / SZ）

leviathanist

崗位有效期至August 31,2018  符合條件的可嘗試,成功率大

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Title: Principal Application Engineer (Physical Design Service)
Location: Shanghai

Position Description:
1.To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
2.To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, for challenging low power designs, for 200MHz to several GHz big chips.
3.Have real design experience including conformal check, logic synthesis, P&R, CTS, SSTA, MMMC to close timing, power and die area.
4.Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
To play a leading role among other team members, while receive little instruction on routine and general assignments.

Position Requirements:
1.A bachelor's degree is essential and 6+ years’ experience in IC design, electronic engineering or computer science applications.
2.Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
3.Requires working knowledge of one or more programming languages, and effective communication and soft skills.
4.MS degree and/or working experience in multi-nation IC design house is a plus.

Title: Lead Application Engineer (Digital Backend)
Location: Shenzhen

Position Description:
1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs.
3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis.
4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
5. To play a leading role among other team members, while receive little instruction on routine and general assignments.

Position Requirements:
1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications.
2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
3. Requires working knowledge of one or more programming languages, and effective communication and soft skills.
4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus.
5. Good communication in English and good work attitude.
6. Be familiar with shell/Perl/Tcl etc. script language.

Title: Lead / Senior Application Engineer (Front-end Verification)
Location: Beijing

Position Description:
1.Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
2.Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
3.Train, ramp-up and accompany customer project.
4.Conduct basic and advanced trainings, presentations and demos as necessary.
5.Providing technical expertise to address clients’ queries, which need expert involvement.
6.Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:        
1.Over 3 years’ experience in the following areas:
2.Design experience in Verilog/VHDL for IP or SoC chip level.
3.HW verification with knowledge of System Verilog/VHDL and HDL simulators
4. FPGA prototyping project experience
5.Experience with hardware emulator or accelerator is a big advantage
6. Advanced Verification Methodology like UVM is a plus
7. Knowledge of Unix and Linux is highly desired
8.Strong verbal and written communication skills in English
9. Strong teamwork skills with good human relationship

leviathanist

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