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Position: Front-enddesign Senior Engineer, Beijing Role &Responsibilities: -
Responsible for Front-End chip implementationincluding design, implementation and execution of the flow that starts with RTLcode and ends with the delivery of a netlist package ready for physical design. -
Responsible for ASIC design methodology and flowdevelopment, interfacing with EDA vendors on technology. Skills andExperience: -
MS degree in Electrical Engineering,Mathematics, Computer Science, or equivalent education background, MS with morethan 3-5 years or Bachelor with more than 5-8 years of industrial experience. -
Familiar with Verilog RTL design and hasexperience of large digital ASIC project. -
Familiar with front-end EDA tools and flows(Design compiler, PrimeTime, Conformal,Verde) -
Familiar with unix/linux and scripts (tcl, perletc.) -
Strong sense of task scheduling and deliver ontime as predetermined milestones committed to manager -
Good English required both verbal and written How to Apply? E-mail to [url=]zhi.lin@amd.com[/url]to inquire details or apply for the position or add wechat via linzhihere |