在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 578|回复: 0

[招聘] MTS/Sr. ASIC simulation analysis/software engineer (Graphics Performance)

[复制链接]
发表于 2018-5-21 11:54:34 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
We're hiring ! If you have any interest , sending email to nina.zhang@amd.com


Job description:

- Co-Work with World Wide Performance analysis and Design Team

- In post-silicon:

1. Work with SW/HW team to analyze the benchmark/Game performance

2. Check/Optimize chip setting for better performance

3. Performance compare/analysis with the competitors’

4. Develop performance analysis/model tools for post-siliconworkflow

5. Performance analysis for each renderingalgorithm in game/benchmark

6. Research new GPU architecture toimprove performance

- In pre-silicon:

1. Simulate rendering algorithm on RTL model to research/analyzeperformance issue on new GPU architecture

2. write demo performance case based on algorithmanalysis result


Minimum requirement:

- Proficient inEnglish read/write/speaking/listening

- Must at least meet 1condition below:

1. Master in Computer Science, Engineering,Mathematics, Physics, EE

2. Bachelor (with 2.5+ years’ experience) inComputer Science, Engineering, Mathematics, Physics, EE

3.
Bachelor with 2+ years’ experience on Graphics/GPU/GPGPUrelated field with relevant industry experience required.

- Must at least meet 1condition below:

1. 3+ yearsof project experience on python/perl

2. 2.5+ years of project experience onC/C++

3. any experience withOpenGL/DirectX3D/GPGPU (driver/shader compiler or game engine... develop/debugwork experience) (highrecommended)

4. 6+ years of experience on linux shell

5. project experience with devicedrivers or compiler(graphics, networking)
(high recommended)

6.
4+years of embedded HW design

7. any research or develop experience relatedto GameEngine/Renderman/MentalRay/GI renderer (highrecommended)


8.
>=2.5 years of HW verification ordesign experience(ASIC or FPGA), familiar with RTL design or timing analysis (highrecommended)

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-7-8 06:02 , Processed in 0.013157 second(s), 8 queries , Gzip On, MemCached On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表