马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
公司内部推荐,职位空缺,急招。有兴趣请发邮件至:ian.xiang@amd.com
Job Responsibilities: ·Develop micro-architecture specification for GPUblocks. ·Develop RTL code for GPU blocks in Verilog HDL. ·Responsible for Front-End chip implementationincluding design, implementation and execution of the flow that starts with RTLcode and ends with the delivery of a netlist package ready for physical design. ·Responsible for ASIC design methodology and flowdevelopment, interfacing with EDA vendors on technology. .
Job Requirements: ·Familiar with Verilog RTL design and has experience of large digital ASIC project.
·Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
·Familiar with unix/linux and scripts (tcl, perl etc.)
·Fluent English on talking, presentation and writing documents.
·Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. |
|