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简历请发到: icpeter@sina.com Job Responsibilities:
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Develop micro-architecture specification for GPUblocks. ·
Develop RTL code for GPU blocks in Verilog HDL. ·
Responsible for Front-End chip implementationincluding design, implementation and execution of the flow that starts with RTLcode and ends with the delivery of a netlist package ready for physical design. ·
Responsible for ASIC design methodology and flowdevelopment, interfacing with EDA vendors on technology. .
Job Requirements:
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Familiar with Verilog RTL design and has experience of large digital ASIC project. ·
Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde) ·
Familiar with unix/linux and scripts (tcl, perl etc.) ·
Fluent English on talking, presentation and writing documents. ·
Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. |
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