Cadence 招聘数字后端设计工程师

kengteng

Title: Principal/Lead Design Engineer (数字后端设计)

Job location: Shanghai/Beijing

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Ifyou have interest, PLS send your update CV to job_china@cadence.com

Titlerincipal/Lead Physical Design Engineer

Position Description:

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Perform physical design implementation,including floor planning, power grid design, place and route, clock treesynthesis, timing closure, power/signal integrity signoff, physical verification(DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

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Thecandidate will have the opportunity to work on many varieties of challengingdesigns, i.e. low power and high speed design. The responsibility includesparticipating in or leading next generation PHY IP physical design, methodologyand flow development.

Position Requirements:        

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BSdegree with 5~10+ years of applicable experience, MS degree with 4~8+ years ofapplicable experience in electrical engineering, microelectronics. Experiencedwith ASIC design flow, hierarchical physical design strategies, andmethodologies and understand deep sub-micron technology issues. Solid knowledgeon LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physicalverification, DFM. Successful track records of taping out complex,16nm/10nm/7nm chips. Automation and programming-minded, solid coding experiencein Makefile/Tcl/Tk/Perl. Self-motivated, able to work independently or as ateam player, excellent verbal and written communication skills in English.