【英伟达上海招聘】ASIC Power Engineer

Nvidia_Staffing

level和salary均open，投递邮箱：nahu@nvidia.com

Position title: ASIC Power Engineer

职位简介：

·
与design工作密切挂钩

·
能更全面的了解chip生产过程中从前端到后端的整个过程

·
接触所有相关team，能扩宽知识领域及对应skill sets，锻炼全面

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对chip的贡献更直观：design→how to make better design

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Careerpath: 接触到chip生产的所有流程，可以真正了解自己的兴趣所在

→EDAtools

→Verification

→Backend

→Power

Shanghaipower team is responsible for researching power expenditures and workloadefficiency to identify architectural, micro-architectural strategies for poweroptimization. We want to hire promising talent who can handle project(s)individually/collectively and also add new dimension to the team.

Responsibilities:

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Create a methodology/algorithm to evaluate power efficiency on high-level(architecture) designs.

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Support IP designers using the power flow to do the power scrubbingwork and improve their power efficiency on micro-arch (ASIC) level.

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Understand and perform block level and chip-level power analysis.

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Communicate/Cooperate with local and abroad teams with power-relatedprojects.

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Co-work with power ARCH team/IP team to evaluate new low-power technologiesand improve chip power efficiency.

Requirements:

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MSEE/MSCS postgraduate.

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Experience in ASICdesign/verification, low power knowledge is a strong plus.

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Must befamiliar with at least one of the programming languages, C/C++ (preferred), Python,Perl.

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Excellent English writing/speaking skills are desired.

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Good communication skills.