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[招聘] 硅谷大牛创业企业-Ours Technology 热聘: RTL/DV Architecture

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发表于 2017-5-24 09:22:19 | 显示全部楼层 |阅读模式

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本帖最后由 caroldou 于 2017-5-24 14:21 编辑

简历投递:caroline.dou@nlvc.com

Company introduction

OURS Technology is a Silicon Valley VC-backed startup founded by PhDs from Berkeley ASPIRE lab. We are building system sensor fusion solutions with our custom silicon for future autonomous driving and robotic applications. When continued scaling is no longer possible, we believe new energy efficient architecture and advanced photonics I/O along with full-stack hardware/software co-design is the future to transform industries. Our team is led by Dr. Zhangxi Tan, who was a founding engineer of Pure Storage (NYSESTG). You will be working in a small but very collaborative environment under guidance of industry veterans in the valley.



RTL/Architecture/DV Engineer

Low-power CPU data path and memory system designs, microarchitecture and design verification. You will be responsible for building chip design infrastructure, architecture/microarchitecture design as well as pre/post-silicon verifications and bring ups.



Requirement:

  • 1. Extensive knowledge on microprocessor architecture and digital circuit designs
  • 2.        Experience in FPGA/ASIC logic synthesis and simulation tools, such as VCS, Primetime, DC
  • 3.        Familiar with timing and power analysis
  • 4.        Knowledge on analog circuit, low-power designs, clock and power gating
  • 5.        Extensive FPGA/ASIC design experience with Verilog/Systemverilog
  • 6.        Experience in scripting languages, e.g. Python, Perl and etc.
  • 7.        Master in CS/EE with relevant project background


Preferred:

  • 1.        Experience in production silicon tape-out
  • 2.        Experience in working with backend design services
  • 3.        Experience in IP integration, memory compiler
  • 4.        5+ years industry experience, lead designers of production chips
  • 5.        Functional language programming with Scala
 楼主| 发表于 2017-6-6 15:58:35 | 显示全部楼层
顶一下
发表于 2017-6-10 01:49:54 | 显示全部楼层
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