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Cadence 上海/北京招聘数字前端实现工程师，有意者请将简历发至541515639@qq.com， 请在邮件标题中注明应聘职位。
Position Description: •In charge ofDDR and HBM IP Front End Implementation. •Daily dutiesinclude: RTL design Integration, Logic Synthesis, DFT, Static Timing Analysisand Verilog Simulation. •HDL languageKnowledge, like verilog is necessary. •C/C++/perl/tcl/csh/python,UNIX, Linux experience are plus. •Excellentanalytical and problem-solving skills. Quick learner-able to learn and applytechnical and complex topics. •Excellentcommunication skills and the uncanny ability in a cooperative team environmentare required. •Self-motivated,result-oriented, can take ownership and follow-through on tasks. Position Requirements: Essential Qualifications: •Masterdegree or above, 2-5 year working experience •Major inMicro-electronics, Electronic Engineering, Computer Science, InformationTechnology or equivalent •Ability towork effectively alone or as well as in the team. •Essentialthat the individual demonstrates strong communication, verbal and written •Requiresgood communication skills in English. Desirable Qualifications: •Good at anyfollowing skill sets: ASIC design, FPGA design, Computer architecture, SOCdesign based on ARM/MIPS. •Experienceof DDR or memory IPs | 
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发表于 2016-8-24 15:46:24
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