AMD上海研发中心招聘——2016年1月最新热招职位

RecruiterAMD

虚位以待，各位大拿敬请投递简历至：zoe.yu@amd.com
投递的时候烦请注明： 姓名+应聘职位+EETOP

Job  Title	Core  Qualification Required
1. Sr./MTS Windows Driver Engineer	1.  Strong C/C++ programming expereince     2. Experience of kernel mode programming under Windows 7 or later     3. Experience of device driver programming under Windows(WDF or KMDF)
2. Sr. Multimedia Driver/Firmware Engineer	1.  Understanding of X86 architecture, be familiar with video processing like  Encode/Decode etc     2. Strong knowledge and past experience on video codecs, such as MPEG-1,  MPEG-2, H.264 and H.265 is required     3. Experience and skills on user mode driver debugging and development is  required
3.Sr./MTS ASIC Verification Engineer	•  Excellent knowledge of design verification methodology, such as OVM/UVM,  systemverilog     • Solid experiences with simulation model creation and the testbench  build     • C/C++ software development experiences is a plus
4.Sr./MTS/SMTS Physical Design Engineer	1.  MSEE with 6+ years or Bachelor with 8+ years of industrial experience in ASIC  design     2. 5+ years or more years of experience in physical design of deep  submicron digital ASIC chips     3. Hands on experience in large scale ASIC chip physical design
5. MTS Engineer for front-end integration	1.  Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+  years working experiences in ASIC Company.     2. familiar with one or more ASIC flows (logic synthesis, STA, formality  check, Design for Power ) and usage of related EDA tools.     3. Familiar with script languages((tcl, perl etc.) in unix/linux.
6. SMTS System Design Engineer	1.  Familiar with X86 architecture (CPU, chipset, I/O devices, etc) and knowledge  of PC architecture.     2. 5+ years’ experience on driver or BIOS debug and/or design     3. Experience of using WinDebug, 3rd party Windows application/tool for  system debug. Be capable of using HW instrument (Oscilloscopes, Logic  Analyzers etc.) for issue analysis is a plus.
7.Sr./MTS AISC Design Engineer	1.Master  with 2+ (or Bachelor with 4+) years working experience in ASIC area     2.Micro-processor (e.g. ARM) architecture and peripheral; Popular on-chip  bus (AMBA/AXI) or NOC; low power  design and verification methodology; Standard IO IPs, including SPI/SMBUS/GPIO/I2C/I2S/UART; DFT/JTAG,  etc.     3. Knowledge on synthesis, timing analysis, CDC and formal verification
8.Sr./MTS DFT Engineer	1.  Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro  test logic.     2. Perform verification on all DFT structures     3. Generate DFT related timing constraints and work with PD team for timing  closure
9. (应届生)ASIC DFT Engineer	1.  Master degree in EE, CS or related     2. Knowleadge of ASIC; Knowleadge of DFT is a plus     3. Good communication skill
10. (应届生)ASIC Verification Engineer	1.  Master degree in EE, CS or related     2. Knowleadge of ASIC Verification     3. Good communication skill