【NVIDIA上海热招】ASIC PD 后端工程师

NVHR

一．公司简介

       NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000名员工，总部在加利福尼亚州圣克拉拉。

工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】

二．投递方式

简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com；请注明来源及申请职位

三．职位详情

1. ASIC-PD Engineer/Senior ASIC-PD Engineer

Job Description:

The ASICPhysical Design engineer is a challenging and cutting-edge position. It hasresponsibility for a wide range of task, including full chip layout planning(partitioning, planning clock distribution and other structure, methodology),partition/full chip timing closure (primetime scripts, other tools, etc) andgate-level design of high-speed logic
Responsibilities:

·RTL Analysis and Synthesis

·Formal verification and netlist quality analysis

·Physical Integration and early floorplan

·Partition level and full chip level StaticTiming Analysis

·Work in conjunction with Place and RouteEngineers to achieve timing closure for both partition level and full chiplevel

·Develop custom timing scripts using tcl/primetimefor clock skew analysis, special circuits such as clock dividers, core logic<-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.

·Cross talk Analysis

·Develop and enhance entire physical design flowfrom frontend (pre-layout) to backend (post-layout) at both chip and blocklevel.

·Develop scripts for performing ECO's.

Basic Requirements:

·BS or MS in Electrical Engineering or ComputerScience

·Above 3 years of relevant ASIC experienceideally with a focus in the physical integration/synthesis/formal and timing closure

·Excellent scripts skills

·
Excellent written and verbal communicationskills in English

·Ability to multiplex many issues, set priorities,and work in a team environment

·Keep up to date with leading edge technologies

BestRegards,

YvetteShen

APACStaffing Team

NVIDIASHANGHAI

Building 2, No. 5709 ShenjiangRoad (No.26 Qiuyue Road)  201210.

Tel+(86 21) 61043660

yvettes@nvidia.com