谱瑞集成电路（上海）有限公司 社招 IC验证工程师 两年以上工作经验优先

zhuyeyi

公司简介
Parade Technologies, Ltd. is a leading supplier of mixed-signal ICs for a variety of popular display and high-speed interface standards used in computers, consumer electronics and display panels. The fabless semiconductor company was founded in 2005 and publicly listed on Taiwan's GreTai Securities Market (GTSM) in 2011 (stock code: 4966 quote). Parade's portfolio of IC products serves the growing demand for HDMI?, DisplayPort?, SATA, and USB ICs for display, storage and interface applications.
In addition to being a technology innovator, Parade is an active participant and leader in industry standards-setting organizations. Parade Technologies, Inc., a wholly owned US-based subsidiary of Parade Technologies, Ltd., is a member of VESA (Video Electronics Standard Association). Parade Technologies, Inc. has made key contributions to the development of VESA's DisplayPort digital video interface standard.
Parade leverages its close relationships with market leading Tier-1 OEMs to develop ICs that provide unique system capabilities. Many of the company's devices integrate proprietary technologies that offer superior system signal integrity, advanced system integration and enhanced power efficiency. As a result of the company's standards-plus design philosophy, Parade ICs have been designed into products offered by nearly every leading computer and display vendor worldwide.
Parade Technologies, Inc. is located in Santa Clara, California, the heart of Silicon Valley, and its primary design center is located in Shanghai, China. The company has a subsidiary in Seoul, South Korea that provides customer support, a branch office in Hong Kong that provides administrative and logistical services, and a branch office in Taiwan that includes a design center and provides sales and customer support, as well as production management and assistance.

职位描述：
职位描述:
RESPONSIBILITIES:
- Develop and execute verification plan
- Develop and maintain verification environment from unit level to system level
- Define and implement functional/code coverage plan
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation
- Develop testing and regression methodologies for new verification flow
- Develop/maintain/enhance environment tools/scripts/makefiles
REQUIREMENTS:
- Proficient and experienced with the C/C++ program
- Experience in asic design or verification
- Proficient with verilog hdl - Proficient with one or more scripting languages, such as Shell, Perl and TCL
- Familiar with logic simulators and debug tools (VCS, NC-Verilog, Verdi etc)
- Familiar with hardware verification language(Vera, Specman-E, SystemC, SystemVerilog), SystemVerilog is a strong plus
- Skill on Makefile is required
- Experience with Verilog PLI is a plus
- Master degree in Electrical Engineering/Computer
CITY:
Nanjing/Shanghai
联系方式：
Mobile Phone:18762680287
QQ:610742994
Email:jing.lu@paradetech.com