【NVIDIA全职】7月份硬件类岗位汇总（ASIC/版图/验证）

NVHR

Hi,All

这边是NVIDIA HR Tracy，目前我们在上海招聘硬件岗位如下，有意向者欢迎发送简历到  tracyw@nvidia.com  qq：1751315121

公司介绍
http://www.nvidia.cn/object/about-nvidia-cn.html
在二十年的时间里，NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。
凭借我们发明的 GPU ——现代视觉计算的引擎，这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。
现在，视觉计算正变得越来越重要，它影响着人们与科技之间的互动方式。

公司地点：上海市浦东新区秋月路26号 （靠近广兰路地铁站）

职位列表：

1. ASIC Design Engineer-上海   

2. ASIC Verification Engineer-上海

3.Mask Layout Engineer-（版图设计工程师）-上海

详细职位描述：

1.ASIC Design Engineer
Key responsibilities:
Ø   understand industry new tech feature requirements and write Micro Arch doc and SW programming guideline.
Ø  Implement RTL design, func debug, synthesis and timing, emulation debug support.
Ø   Key requirements:
Ø   BS or above degree in EE or related area with solid knowledge base.
Ø   3+ years of working experiences in ASIC design.
Ø   Strong Verilog programming ability, familiar with all kinds of frond-end ASIC design flow & design tools.
Ø   Knowing display tech like HDMI/DP/DSI/pixel processing is a big plus
Ø   Fluent English (both written and spoken) and excellent communication skills
Ø   Demonstrated ability to work independently as well as in a multi-disciplinary group environment

2. Verification Engineer
ASIC Verification Engineer
Responsibilities:
The Sr. verification engineer is expected to cover testbench setup, familiar with verif flow and tracking strategy.
Minimum Requirement:
- BS/MS in electrical/computer engineering and related.
- 3+ years MS or 5+ years BS
- Excellent perl/C++ skills
- Complex TB setup experience.
- Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
- Good understanding in Verilog and project tree infrastructure.
- Makefile is big plus
- Fluent English (both written and spoken) and excellent communication skills
- Demonstrated ability to work independently as well as in a multi-disciplinary group environment

3.MASK Layout Engineer
Job Description/Qualifications:
RESPONSIBILITIES
- Convert Schematic drawings to physical layout views for Standard and Data Path cells, and embedded SRAM in deep sub-micron CMOS process under Cadence environment.
- Layout floor plan for both cell level and macro level.
- Layout verification including DRC(DFM)/ERC/LVS.
- Layout data base and version control, and FRAME view generation.

MINIMUM REQUIREMENTS:
- BSEE or above.
- years or more relevant experience.
- Familiar with Cadence design environment.
- Experience Layout verification with Hercule/Calibre/Magma.
- Be able to estimate schedule on the assigned task.
- Basic knowledge of transistor devices.
- Unix system and commands.
- Good communication in English.
- Place and Route knowledge is a plus.

Best Regards

Tracy