MASK Layout Design Engineer
Job Description/Qualifications:
RESPONSIBILITIES
- Convert Schematic drawings to physical layout views for Standard and Data Path cells, and embedded SRAM in deep sub-micron CMOS process under Cadence environment.
- Layout floor plan for both cell level and macro level.
- Layout verification including DRC(DFM)/ERC/LVS.
- Layout data base and version control, and FRAME view generation.
MINIMUM REQUIREMENTS:
- BSEE or above.
- 1 year or more relevant experience.
- Familiar with Cadence design environment.
- Experience Layout verification with Hercule/Calibre/Magma.
- Be able to estimate schedule on the assigned task.
- Basic knowledge of transistor devices.
- Unix system and commands.
- Good communication in English.
- Place and Route knowledge is a plus.
Tracy
APAC Staffing Team
QQ: 1751315121
021-61043650