后端

jj_seu

Automatic Placement and Routing(APR)Engineer@上海

也叫Physical Design/后端/Backend

可以去台湾培训3个月的后端机会

简历发真芯的芯得  hr@hi-talent.com  

Job Description:

1. Be responsible for advanced chipimplementation flow development, chip PPA boost, and support headquarteradvanced technology for EDA router engagement.

2. ASIC block-level implementation and/orfull-chip integration projects.

3. Develop IC design methodology.

Qualifications:

1. MS or PHD in CS,EE related field with3-4 years experience in APR, physical verification, chip implementation, or CADalgorithm.

2. Expert in ASIC RTL-to-GDS design flow.

3. Solid skill sets ofCadence/Synsopsys/Mentor EDA tools.

4. Experience with TSMC 40nm technology.

5. Experience in implementation signoff.

6. Proven record in production tapeouts.

7. Experience in tapeout with multi-milliongates count SOC design. 28nm/40nm design experience is a plus.

8. Capable of executing timing budgeting,synthesis, P&R, CTS,

timing closure, DFT, physical verification,DFM and spice simulations.

9. Experience in CAD methodology andproblem solving skill.

10. Familiar with Verilog, Perl/Tcl andC/C++.

11. Good communication in English.

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

Mob:           18502155252

E-Mail:         Jane-Jin@hi-talent.com

微信：      xinde_jane

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Weibo:          http://weibo.com/u/1716864892

webside：     www.hi-talent.cn