【社招】合肥IC design职位招聘

FlowerSun0326

职位描述: IC Design and Integration 工程师(2人)

注意：这个职位属于中前端+后端都要的

简历发 “芯”上人  芯得 hr@hi-talent.com
809955316@qq.com

- IC前端设计及SOC系统工作，包括rtl coding，design综合，静态时序分析及收敛，芯片整合及验证相关工作

- 使用Synopsys/Cadence/Mentor公司如DC/DFT/STA/MBIST等tool进行前端flow

- 使用Perl, TCL, Awk和Sed等脚本语言进行部分tool job的整合以及相应report的分析

- 和前端IC设计师及后端物理工程师协同工作, 协调进行SOC时序收敛.

- 规划SOC 低功耗设计

- 对于DFT,定义IC测试规格与方法

- 编写相关脚本或进行MBIST, SCAN (包括stuck at, at speed), 边界扫描，模拟IP测试电路的生成

测试电路的验证，测试向量的生成

- 与测试厂家合作，制定监视测试流程





综合素质要求:

- 良好的沟通能力和团队合作精神

- 高度的责任心和敬业精神

- 较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力

- 较强的英文能力



专业背景要求:

- 电子工程、计算机科学或相关学科本科以上学历, 硕士(含)以上学历者优先

- 熟悉Verilog或VHDL硬件design 语言

- 熟练TCL编程,perl，sed和awk脚本语言

- 熟悉IC design和前端flow check的tool，如（Synopsys / Cadence / Mentor）的DC/DFT/STA/MBIST等

tool的使用

- 熟悉40nm或28nm及以下process SOC设计

- 熟悉IC综合及scan chain insertion相关知识，使用过STA进行timing静态时序分析

- 有SOC system前端整合工作经验者优先，非必须

- 熟悉IC生成测试流程

- 本科至少三年，硕士至少一年 IC设计相关工作经验





Job Description IC Design and Integration engineer (2)

简历发 真芯人 芯得 hr@hi-talent.com

- IC logic design (Front End) and SOC system work, including Verilog RTL coding, Synthesis,

Static Timing Analysis and Closure, SOC Integration and Verification related work

- Use Synopsys/Cadence/Mentor EDA tools, such as DC, DFT, STA, MBIST, etc to do FE design flow

- Use Perl, TCL, Awk and Sed script language to integrate parts tools job, and process report,etc

- Work with FE IC designer and BE IC designer (Physical Designer), Check design function and timing quality, coordinate SOC static timing closure.

- implement SOC Low power design structure

- Write test structure specification

- Implement and verify tasks of MBIST generation, scan insertion, boundary scan, TAP controller

generation, analog testing, and test pattern generation

- As an interface to test vendor in IC production testing.



General Qualifications

- Good communication capability and teamwork spirit

- High degree of initiative and responsibility

- Logical thinking and sensitive to the problem with good self-study and problem shooting ability

- Good English capability



Experience

- Bachelor’s degree in Electrical Engineering, Computer Science, or related discipline (Masters

preferred).

- Familiar with verilog or VHDL hardware design language

- Familiar with TCL/Perl/Sed/Awk script language, etc

- Familiar with FE design and flow tool, know about Synopsys/Cadence/Mentor IC tool, such as

DC, DFT, STA, MBIST, etc

- Be familiar with SOC design flow in 40nm, 28nm and below process

- Familiar with IC synthesis and scan chain insertion related knowledge, have experience in

timing analysis with STA

- Experience with SOC integration is preferred, but not must

- Familiar with production test flow

- Bachelor had 3+ years and Master had 1+ year IC design field experience