推荐一个研究STT-RAM用的模型

smartzmz

给大家推荐一个研究STT-RAM用的模型，可以模拟不同MTJ配置下STT-RAM的延迟和功耗特性。
模型由University of Virginia开发，使用hspice 2011编译 mtj_hplp_1.0.0.zip (80.2 KB, 下载次数: 24 )

2015-3-11 11:22 上传

点击文件名下载附件
stt-ram模型

dcircuit

下来看看

HenryZhao

你好，我怎么运行时报错呀？
hsp-vacomp: Warning: Variable 'min_float' in module 'ElectronTrans' is never set.

hsp-vacomp: Warning: Variable 'min_float' in module 'IncUpTransDown' is never set.

hsp-vacomp: Warning: Variable 'min_float' in module 'IncUpTransUp' is never set.

hsp-vacomp: Warning: Variable 'min_float' in module 'IncDownTransUp' is never set.

hsp-vacomp: Warning: Variable 'min_float' in module 'IncDownTransDown' is never set.

hsp-vacomp: Error: Nodes which are accessed must have a discipline specified.

hsp-vacomp:         ['MTJ.va',200]


** error **
During Verilog-A Device processing:
    Failed to compile the Verilog-A File,
        'c:\users\zhy\desktop\eetop.cn_mtj_hplp_1.0.0\MTJ.va'.

  lic: Release hspice token(s)
你遇到过这种情况吗？

寒兆

你好，运行时报错了这种算是什么情况？
hsp-vacomp: Synopsys HSPICE Verilog-A Compiler Version 1.52.021608.

hsp-vacomp: Copyright (C) 2008 Synopsys, Inc. All Rights Reserved.

hsp-vacomp:

hsp-vacomp: Error: syntax error

hsp-vacomp:         ['MTJ.va',24]

hsp-vacomp:           real rand_noise = 0.0;              //Random number sequence variable

hsp-vacomp:                           ^


** error **
During Verilog-A Device processing:
    Failed to generate the loadable component names file from the Verilog-A File,
         'MTJ.va'.


               ***** job aborted


还有，MTJ.va文件中，
`include "disciplines.vams"
`include "constants.vams"
这两个文件是什么？怎么没有？

Desingman

下来看看