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Cadence SH 招聘资深数字后端产品工程师 更多职位信息敬请关注Cadence公众微信平台:Cadence中国招聘 If you have interest, PLS send your update CV to zhangyl@cadence.com 1.PrincipalCustomer Engagement Engineer-数字后端 PositionDescription: 1.The primary responsibility is designing,developing, troubleshooting and debugging software programs on Unix/Linuxplatforms. 2.Be involved in developing software tools foradvanced chip design platforms. 3.The responsibilities also include engagingwith customers in understanding their ASIC design requirements fornano-technology process nodes and assisting them in adopting Cadence designplatform and helping them in performing successful tapeouts of theirSystem-on-chip designs using the same. 4.The job will also involves presenting anddemonstrating relevant Cadence technologies and carrying out productevaluations, workshops, trainings and competitive replacement campaigns. PositionRequirements: 1.The candidates should have strong in-depthP&R design experience in COT or ASIC area. 2.Experience and ability to get solutions inFloor plan, Power Planning/Analysis, CTS, timing optimization/analysis, signalintegrity and DFM issues (DRC & Antenna) is a MUST. Strong interest andunderstanding of design methodologies are required. 3.Need to have good knowledge on VDSM (40nm andbelow) processes issues. 4.Good verbal and written presentation are must. 5.Hands-on Cadence Encounter experience is a bigplus. 6.Minimum master degrees in EE or CS. 2. 产品验证工程师 - 数字后端 职位描述: (1)
验证数字后端EDA工具Encounter,确保产品在整个后端设计流程中可以正确工作 职位需求: (1)
熟练掌握微电子专业的基础知识 (2)
熟悉IC设计流程,有使用EDA工具(Cadence/Synopsys/Magma/Mentor)经验者优先 (3)
熟悉Linux/Unix工作环境,熟悉perl/tcl/csh等 (4)
具备良好的自学能力和团队协作精神。 (5)
本科及以上学历,英文读写流利,听说熟练。 3.高级/产品工程师 职位描述: (1)
负责Unix/Linux平台下软件的设计、开发和维护,参与先进芯片后端软件工具的研发。 (2)
与客户进行沟通,理解客户在纳米工艺下的ASIC设计需求,协助客户熟悉Cadence设计平台,对客户的SoC设计提供支持和帮助。 (3)
负责介绍说明Cadence的相关技术,开展产品的评估、研讨以及培训。 职位需求: (1)
精通布局布线、电源规划、功耗分析、时钟树综合、时序优化及分析、信号完整性、可制造性(包括设计规则检查以及天线效应)等后端流程。 (2)
对后端设计有浓厚的兴趣和深刻的理解。 (3)
熟悉超深亚微米工艺(40nm及以下)。 (4)
具有较强的语言沟通能力。 (5)
熟练操作Cadence Encounter者优先 (6)
电子工程或计算机相关硕士及以上学历。 |