Cadence招聘资深前端验证/设计工程师

kengteng

Cadence招聘资深前端验证/设计工程师

Title: Principal/Lead/Senior Verification Engineer(数字前端验证)

Location： SH/BJ

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your updateCV to zhangyl@cadence.com

  

Position Description:

Deliver/implement advancedverification solutions by utilizing Cadence’s Incisive Verification productportfolio. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

-- Deep understanding onASIC/SOC design flow

-- Excellent knowledge ofadvanced verification methodology like eRM/OVM/UVM

-- Familiar with Cadence’sIncisive Plan to Closure Methodology (IPCM)

--Proficiency in SystemVerilog,  System C and/or e (Specman)

-- Developing and usingVerification Components (eVC, OVC, UVC, VIP)

-- Developing and usingassertion based verification and formal analysis methods

--Skilled in scriptinglanguage, such as Perl, C shell, Makefile

-- Assessing the projectverification requirements

-- Operating in a lead roleregarding architecting and implementation of project   

     verification environment/solution.

-- May coordinate/leadothers within the scope of a defined project

Position Requirements:

-- Must have BS degree with 6+ years of applicable experience, MS degreewith 4+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.

-- Essential that theindividual demonstrates strong communication, verbal and written. Requires goodcommunication skills in English.

Desirable Qualifications:

-- A minimum of seven yearsrelevant experience in industry.

-- Will have demonstratedhands-on experience and expertise with Cadence verification design tools orequivalent tools, flows and methodologies required to execute a verificationproject.

-- Will have demonstratedsuccessful completion of 10+ verification projects as an individual contributor

-Prefer to have DDR IPverification experience

Title: Lead/Senior Design Engineer (数字前端设计)

Location: SH/BJ

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your updateCV to zhangyl@cadence.com

Position Description:

Deliver/implement DDR IP. The engineer should beable to act as a strong team member and contributor, leading team projects andinitiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:

- Be responsible for building and leading ahigh-performance IC design team, owning the IC micro-architecture, package andtest platform development, refining the EDA design flow

- Proficiency in logic design, simulation,synthesis, STA and testing

- Proficiency in Verilog and its simulationenvironment

- Good knowledge of IC design

* At least five years experience driving complexIC development projects, excellent communication skills and the uncanny abilityto both lead and contribute in a cooperative team environment.

  

Position Requirements:

1. Essential Qualifications: Must have BS degreewith 6+ years of applicable experience, MS degree with 4+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics.

2. Essential that the individual demonstratesstrong communication, verbal and written. 3. Requires good communication skillsin English.