武汉急招职位 Synopsys ASIC Design/Verfication Engineer_DDR PHY

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The ideal candidate will have good background in RTL design and directed verification. Design expertise includes understanding Standard Specifications/micro-architecture documents, ability to design for low area/power; Designer should have understanding of good coding guidelines. Directed Verification expertise includes knowledge of verification concepts, definition of verilog testbench, test case development and verifying the design under test. Also the candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases.
Job responsibilities include understanding DDR memory system and working on the design/directed verification of DDR design. Be able to implement test benches and test cases in hdl like Verilog is needed. The candidate will work in a project and team oriented environment with teams spread across multiple sites worldwide.

Have BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:
-Hands on experience with Verilog coding and Simulation tools
-Prior asic/IP directed verification skills with essential knowledge of Verilog/ System Verilog
-Synthesis flow and static timing flows, Formal checking, etc is a plus
-Knowledge of DDR memory system is a plus
-Knowledge of C/C++/System C is a plus
-Experience with Perl/Shell/Makefile scripts is a plus.
In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills.
The candidate will be part of the Solutions Group at our Wuhan Design Center, China. The position offers learning and growth opportunities in Synopsys' new Design Center at Wuhan.

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欢迎投递简历到：zhuqin.tang@synopsys.com