Synopsys (HR) 热招 Verification Manager /DDR CAE

Domiliu

If you have any interest in the position, please send your bilingual resume as attachments to  dmliu@synopsys.com

1\ Synopsys DDR PHY CAE

Location: Shanghai/Shenzhen

http://search.51job.com/job/65266332,c.html

Description

As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers.

Requirements

Qualified applicants will have a BSEE, MSEE, + 5 years relevant experience in ASIC design.

Domain knowledge of the DDR3/2 Protocols with relevant experience is a plus.

Recent experience with ASIC implementation EDA tools and flows in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired.

2\ Job title: Verification Manager

Location: Wuhan

http://search.51job.com/job/65501287,c.html

Description:

Verification is the number one bottleneck in SOC designs today.

Synopsys is uniquely positioned to offer the most complete verification solution in market today.

VCS is the simulation platform for Synopsys verification flow, it incorporates a suite of built-in high performance next generation technologies for test bench automation, assertion based verification, coverage closure, etc., which are needed for verifying challenging multi-million gate designs.

ZeBu is the emulation platform for Synopsys verification flow, it’s the industry’s performance & capacity leader in Emulation.
As a CAE Manager for Emulation/Transactor development, based in Wuhan, candidate will be responsible for leading a team to deliver successful development of emulation transactors and deployment of Synopsys emulation solution(ZeBu) to a growing customer base in AsiaPacific.

The CAE responsibilities include developing transactors covering different protocols, onsite deployment of industry leading emulation technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement.

Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex emulation issues for customers cutting edge ASIC designs.

The position offers a great opportunity to grow by learning state-of-art emulation flows from Synopsys.

Requirements:  

MS or PhD majored in EE with more than 8 years of IC design/verification/emulation experiences. Good knowledge of high-level verification and emulation methodologies and strong communication skills are required.

Ability to work with customers and R&D teams is important. Real project experience in ASIC/SoC emulation or FPGA development and good expertise on popular emulators like Palladium/Veloce/Zebu and Xilinx/Altera FPGA are required. Proficient with HDL (Verilog/VHDL), HVL(systemverilog), C/C++, Unix. Experience on VMM/OVM/UVM and knowledge of VIP/AVIP and simulator-emulator co-emulation are preferred.