灿芯半导体招聘SerDes设计工程师

yudgern

请发邮件至peter.zhou@britesemi.com

Senior SerDes Design Engineer

Job Requirements:

1.
At least 3 or more years of Analog circuit design experience with MS in EE or Physics (more senior levels will also be considered)

2.
Experience on high speed SerDes design or high performance PLL/DLL design or high performance timing circuit is needed.

3.
Experience on DFE/CDR architecture or circuit is a plus.

4.
Willing to work as an active team player with group’s goal in mind.

5.
Familiar with SPICE simulations including Monte-Carlo analysis

6.
Strong knowledge in physical layout and component’s parasitic effects.

7.
Knowledge with process and device physics is a plus

8.
Acceptable communication skill in written and spoken English

9.
Strong passion to learn

Job Descriptions:

1.
Working on the SerDes transceiver design including the flowing circuit blocks: High performance PLL,DFE/FFE/filter, CDR, Equalizer, Serilizer, Deserializer, Phase interpolator, Receiver, Driver, Regulator, High speed clock distribution and so on.

2.
Working on a set of common SerDes standards like USB3.0/USB3.1, SATA3,PCIE,HDMI/MHL, DisplayPort, MIPI,10G-KR,Rapid IO and so on.

3.
Working architecture modeling on CDR/DFE/FFE/PLL with Matlab/verilog A/C

4.
Be responsible for schematic capture, simulation, test plan, DK generation and bench verification/characterizations.

5.
Escort and instruct layout designers to complete physical implementations

6.
Ensure database integrity before any release.

7.
Execute any project assignment in the timing manner.

8.
Follow company’s quality standards during any project execution.