【NVIDIA实习】硬件软件通信各类实习岗位火热招募【可留用】

NVHR

NVIDIA(英伟达) 新一轮实习生项目火热招募中！

想领略全球最先进视觉运算公司的魅力吗？

想和国内外最优秀的IC人才共事吗？

想在职业生涯中获得全面指导和快速进步吗？

想在高尖人才云集的IC行业挥洒青春并实现自我价值吗？

如果您对上述问题有着肯定的答案，还犹豫什么，快来加入NVIDIA(英伟达)实习生项目吧!

一．项目介绍

自实习生作为校园招聘人才储备项目启动至今，每年都有几十名来自各大高校的优秀学生加入我们上海研发中心，与我们的员工一起参与到全球最先进视觉计算技术中，他们中的很多佼佼者已经作为应届生被录取成为NVIDIA正式员工。

二．公司简介

        NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000名员工，总部在加利福尼亚州圣克拉拉。

上海研发中心地址：上海申江路5709号（秋月路26号）矽岸国际2号楼

三．投递方式

请您将的简历命名以及邮件主题命名；命名格式均为：姓名-申请职位-学校专业-毕业时间-周实习天数-实习月数（例如:张三-ASIC Physical Design-上海交大微电子-2016毕业-一周五天-12个月）
投递至HR邮箱：yvettes@nvidia.com

四．招聘岗位

1. DFT Engineer(DFT实习生)

(DFT帮你避开千军万马过独木桥的惨烈申请！)

2. PhysX DEVTECH(软件实习生)

(图像处理，算法，游戏引擎。。。各种高精尖！)

3. ICAFE SoftwareQA Engineer (软件/游戏测试实习生)

(通过玩游戏测试性能，玩游戏还能赚钱有木有。。。)

4. Modem PlatformValidation Engineer (软件/通信实习生)

(英文好，通信类专业是我们的最爱！15、16、17毕业的同学皆可申请，别忘了附上英文简历哦~)

5. ASICDesign/ASIC Verification Engineer (ASIC前端或者ASIC验证实习生)

(2016校招储备大户，2016年毕业的同学们不容错过的好机会！)

6. ASIC-PhysicalDesign Engineer (ASIC-后端实习生)

(2016校招储备大户，2016年毕业的同学们不容错过的好机会！)

7. PR-PhysicalDesign Engineer (PR-后端实习生)

(2016校招储备大户，2016年毕业的同学们不容错过的好机会！)

五．招聘流程

简历投递-电话面试或笔试-Face to Face面试-录用

六．
职位详述

1. DFT Engineer (DFT实习生)
RESPONSIBILITIES:
- Responsible for DFT implementation includingtest mode controllers, IO BIST, Memory BIST/Repair and JTAG based on DFT plan.
- Responsible for scan insertion, ATPG and postsilicon validation.
- Responsible for DFT logic and patternverification.
- Responsible for ATE chip bringup and failureanalysis.

Minimum Requirement:
- BSEE required, MSEE preferred.

- 2+ years of experience in DFT/design field

- Strong logic Design and verificationbackground with experience in STA.

- Must possess a strong knowledge of DFTincluding scan, ATPG, Test Compression, JTAG and BIST.
- Programming in Perl, tcl and C/C++ is a plus

- Good Englisth communication skills
- Self-motivated and good team player

2. PhysX DEVTECH (图形处理相关/软件类实习生)

NVIDIA is seeking an intern to do physics effects R&D work for video games.The R&D fields include:
- Rigid body simulation
- Particle & Fluids simulation
- Cloth & soft body simulation
- Hair simulation

The work is to extend the existing algorithms and to make innovative physicseffects both on simulation and rendering. Another part of the job is tointegrate the effects to commercial video game engines.

REQUIREMENTS:
- Master Degree in Computer Science, Engineering, Physics, or Mathematicalfield
- Strong knowledge of C/C++, programming techniques, and algorithms
- Strong mathematical fundamentals
- Good English communication skill

Recommended Experience:
- PhysX or other physics engine
- DirectX/OpenGL/CUDA

3. ICAFE Software QA Engineer (软件/游戏测试实习生)
RESPONSIBILITIES:
- Functionality testing on NVIDIA icafe product.
- Assist developer to debug and validate onNVIDIA icafe product
- Solve and verify problem from customer andworking with developer to fix the problem

REQUIREMENTS:
- Computer science and related
- Strong data analysis and logical ability.

- Deep understanding on the game and testing isa plus.

- Good communication skill, fluently written andoral English.

- Good skills on PC and network.

4. Modem Platform Validation Engineer (软件/通信实习生)
NVIDIA's site in Shanghai is helping to build aglobal business with the latest mobile communications technologies. We buildmodem solutions which are mainly used in smartphones, tablets and computers.

We are searching for a Modem Platform ValidationEngineering Intern for our Customer Product Validation team. The main functionof this team is to validate the releases we plan to deliver to our customers ondifferent target HWs (smartphones, tablets or computers). The successfulapplicant for this internship will have to validate all the aspects of thedelivery, in an end-user perspective. He/she will have to verify thereliability of the product in terms of protocol aspects. In particular, he/shewill have to check the stability of the product in static conditions on the livenetworks available in Shanghai. His/her opinion about the delivery will helpmanagement team to decide whether the delivery is good enough to be sent to thecustomer.

RESPONSIBILITIES:
- To define a test plan according to theplatform to test
- To prepare the test sessions
- To run the tests thanks to our automatic toolsor manually, depending on the tested product
- To analyze issues and share them withdevelopers
- To track the issues using our database
- To provide a final test report to project team/managementteam
- To give a clear opinion about the delivery,based on the end-user experience with the product
- To participate to the enhancement of our testplans

REQUIREMENTS:
- Academic experience in Telecom Engineering (aprevious internship in the telecommunications area would be a plus).
- Fluency in written and spoken English, withexcellent communication skills.
- Knowledge of the basics ofGSM/GPRS/EDGE/UMTS/HSDPA/HSUPA/LTE standards.
- Ideally, knowledge of Android, Windows on ARMand Chrome OS systems.
- Rigorous, methodically inclined, organized.
- Able to synthesize huge amounts of informationand to work on several activities/projects in parallel
- Autonomous, able to learn quickly and to workin a fast-paced environment
- Ability to work proactively and to contributeto the company?s innovative solutions

NVIDIA is widely considered to be one of thetechnology world?s most desirable employers. We have some of the most brilliantand talented people on the planet working for us and, due to unprecedentedgrowth, we?re always on the look-out for more. If you're a diligent andautonomous engineer with a genuine passion for technology, we want to hear fromyou.

5. ASICDesign/ASIC Verification Engineer (ASIC前端/验证实习生)

REQUIREMENTS:
- BS/MS in electrical/computer engineering andrelated.

- Good skills in Verilog. Solid understanding inRTL sim verification of digital design.

- Perl scripting skills is appreciated as aplus.

- Fluent English (both written and spoken) andexcellent communication skills

- Demonstrated ability to work independently aswell as in a multi-disciplinary group environment

6.ASIC-Physical Design Engineer (ASIC-后端实习生)

As a result of the improvement in chip process, design scale andperformance/power ratio expectation, physical design for digital chips havehuge challenges on high frequency, low power, multiple application modes etc.Effective and high quality implementation of building chips is the guarantee ofthe company’s competitiveness.

As an ASIC-PD engineer at NVIDIA, you'll be responsible for thestage from RTL frozen to tape out, include synthesis, formal verification,constraints definition, timing closure/sign off, study on the timing impact ofprocess and related methodology work. You will face the biggest challenge basedon the most advanced processes on building chips in the world.

RESPONSIBILITIES:

• Chip integration     and netlist generation
• Synthesis
• RTL/netlist     quality check
• Formal     Verification
• Constraints     creation and validation, timing budget.
• Work with ASIC     team to analyze/resolve special timing issues.
• Co-work with PR     engineers to implement chip partition and floorplan
• Work in     conjunction with RR engineers to achieve timing closure for both partition     and full chip level
• Achieve special     mode timing closure, such as io, test, clock etc.
• Function eco     creation
• Develop and     enhance entire timing closure flow from frontend (pre-layout) to backend     (post-layout)
• Flow automation     development for above areas
• Methodology in     any of above areas.

MINIMUM REQUIREMENTS:

• BSEE, MSEE is     preferred
• Project     experience in IC design implementation
• Courses taken in     circuit design, digital design
• Hand-on     experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC     compiler/LEC) is preferred
• Proficient user     of Perl or TCL is preferred
• Excellent     English communication skill

随着芯片工艺不断进步,设计规模的增大，对性能/功耗比期望的提高，数字芯片物理设计面临着高时钟，低功耗，多应用模式等巨大挑战。芯片的高效和高质量的物理实现是公司竞争力的保证。

作为NVIDIA的ASIC-PD工程师，你将负责从RTL冻结到流片这个阶段中综合，形式验证，约束文件制定，时序收敛以及相关方法学和工艺在时序方面影响的研究工作。在芯片实现方面，你将基于世界上最先进的流程面临最大的挑战。

工作职责:

• 芯片集成，网表生成
• 综合，网表质量分析
• 逻辑等价性验证
• 约束文件的创建和验证, 产生底层模块时序约束
• 与前端工程师一起分析解决时序问题
• 与P&R工程师合作完成芯片物理实现模块划分
• 芯片级和模块级时序分析和时序收敛
• 特殊工作模式的时序分析和时序收敛，
  如IO，TEST等
• 产生功能ECO脚本
• 以上领域流程的开发，维护和增强
• 以上领域方法的研究

职位要求:

• 电子工程或相关专业硕士生或本科生
• 有芯片设计经验
• 有相关课程背景：电路设计，数字电路
• 有相关EDA工具使用经验者优先：Synopsys     (DC/PT/Formality), Cadence (RC/LEC)
• 具有脚本编写能力者优先：Perl, TCL
• 良好的英语交流能力

7.PR-Physical Design Engineer (PR-后端实习生)

RESPONSIBILITIES:
- Responsible for flow automation, regressiontest
- Analysis on placement, routing, timing, clock,power, noise and DFM

REQUIREMENTS:
- MSEE
- Basic knowledge of device model, processingtechnology, timing, noise and power in chip design
- Proficient user of Perl or TCL ( or C, Python)is preferred
- Hands-on experience in EDA softwares fromSynopsys (PC/ICC/DC/PT/STAR-RC), Cadence (First Encounter) is a plus