[全职]Synopsys 武汉热招Emulation Manager/Digital IP Designer

Domiliu

If you have any interest in the position, please send your bilingual resume as

attachments to
dmliu@synopsys.com

1\ Job Title: Digital IP Designer ( ASIC Design or Verification_
USB DDR MIPI SATA)

Location: Wuhan

http://search.51job.com/job/53774338,c.html

Job responsibilities include understanding connectivity protocols like SATA, MIPI, SDMMC, AMBA, HDMI and working on the design/directed verification of designs in such protocols.

Be able to implement test benches and test cases in HDL like Verilog is needed.

Requirements:

- Has BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:

- Has good background in RTL design and directed verification. Hands on experience with Verilog coding and Simulation tools

-Prior ASIC/IP directed verification skills with essential knowledge of Verilog/ System Verilog

-Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background

2\ Job title: Emulation Manager

Location: Wuhan

As a CAE Manager for Emulation/Transactor development, based in Wuhan, candidate will be responsible for leading a team to deliver successful development of emulation transactors and deployment of Synopsys emulation solution(ZeBu) to a growing customer base in AsiaPacific. The CAE responsibilities include developing transactors covering different protocols, onsite deployment of industry leading emulation technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement. Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex emulation issues for customers cutting edge ASIC designs. The position offers a great opportunity to grow by learning state-of-art emulation flows from Synopsys.

Requirements:

MS or PhD majored in EE with more than 8 years of IC design/verification/emulation experiences.

Good knowledge of high-level verification and emulation methodologies and strong communication skills are required. Ability to work with customers and R&D teams is important.

Real project experience in ASIC/SoC emulation or FPGA development and good expertise on popular emulators like Palladium/Veloce/Zebu and Xilinx/Altera FPGA are required. Proficient with HDL (Verilog/VHDL), HVL(systemverilog), C/C++, Unix.

Experience on VMM/OVM/UVM and knowledge of VIP/AVIP and simulator-emulator co-emulation are preferred.