在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 1678|回复: 2

[招聘] Cadence招聘Principal/Lead/Senior Verification Engineer (数字前端验证)

[复制链接]
发表于 2014-9-5 14:49:49 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x

Cadence招聘Principal/Lead/Senior Verification Engineer (数字前端验证)

Location SH/BJ


更多职位信息敬请关注Cadence公众微信平台:Cadence中国招聘

二维码.JPG


If you haveinterest, PLS send your update CV to zhangyl@cadence.com

  

Position Description:

Deliver/implement advanced verification solutions by utilizingCadence’s Incisive Verification product portfolio. The engineer should be ableto act as a strong team member and contributor, leading team projects andinitiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:

-- Deep understanding on ASIC/SOC design flow

-- Excellent knowledge of advanced verification methodology likeeRM/OVM/UVM

-- Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)

--Proficiency in System Verilog, System C and/or e (Specman)

-- Developing and using Verification Components (eVC, OVC, UVC, VIP)

-- Developing and using assertion based verification and formalanalysis methods

--Skilled in scripting language, such as Perl, C shell, Makefile

-- Assessing the project verification requirements

-- Operating in a lead role regarding architecting and implementationof project   

     verificationenvironment/solution.

-- May coordinate/lead others within the scope of a defined project

Position Requirements:

-- Must have BS degree with 6+years of applicable experience, MS degree with 4+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics.

-- Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English.

Desirable Qualifications:

-- A minimum of seven years relevant experience in industry.

-- Will have demonstrated hands-on experience and expertise withCadence verification design tools or equivalent tools, flows and methodologiesrequired to execute a verification project.

-- Will have demonstrated successful completion of 10+ verificationprojects as an individual contributor

-Prefer to have DDR IP verification experience

发表于 2014-9-8 22:55:22 | 显示全部楼层
谢谢楼主,楼主辛苦了!
发表于 2014-9-9 22:22:14 | 显示全部楼层
怎么还在招? 几个月前投了简历就石沉大海了,怎么着也得给个回信吧
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-7-5 15:50 , Processed in 0.020560 second(s), 9 queries , Gzip On, MemCached On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表