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Cadence招聘Principal/Lead/Senior Verification Engineer (数字前端验证) Location: SH/BJ
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If you haveinterest, PLS send your update CV to zhangyl@cadence.com Position Description: Deliver/implement advanced verification solutions by utilizingCadence’s Incisive Verification product portfolio. The engineer should be ableto act as a strong team member and contributor, leading team projects andinitiatives. Exercise judgment within generally defined practices and policies. Specific duties include: -- Deep understanding on ASIC/SOC design flow -- Excellent knowledge of advanced verification methodology likeeRM/OVM/UVM -- Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM) --Proficiency in System Verilog, System C and/or e (Specman) -- Developing and using Verification Components (eVC, OVC, UVC, VIP) -- Developing and using assertion based verification and formalanalysis methods --Skilled in scripting language, such as Perl, C shell, Makefile -- Assessing the project verification requirements -- Operating in a lead role regarding architecting and implementationof project verificationenvironment/solution. -- May coordinate/lead others within the scope of a defined project Position Requirements: -- Must have BS degree with 6+years of applicable experience, MS degree with 4+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics. -- Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English. Desirable Qualifications: -- A minimum of seven years relevant experience in industry. -- Will have demonstrated hands-on experience and expertise withCadence verification design tools or equivalent tools, flows and methodologiesrequired to execute a verification project. -- Will have demonstrated successful completion of 10+ verificationprojects as an individual contributor -Prefer to have DDR IP verification experience |