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Description
1. The candidate should be having 3-5 years of experience in full customer Layout design of Analog and IO circuits in recent technology nodes. Preference would be given to 40nm/28nm experience.
2. The candidate is expected to have the required know how in usage of the layouts at full chip level
3. The candidate needs to have strong knowledge of layout concepts, limiting design rules and process know-how
4. Candidate has ASIC APR flow (RTL-GDS) experience will be highly preferred.
5. The candidate needs to have good communication skills to communicate/escalate the issues and get them resolved through support teams.
Qualifications
BE/ME in electrical/electronic engineering stream with 3-5 years of experience in Layout design of Analog and IO circuits in recent technology nodes
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!
“KT人才”微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”即可添加,欢迎大家关注!(关注成功后输入”KT“即可查询职位!) |
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