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发表于 2014-3-28 22:28:07
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Verification Compiler™ provides all of the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs (See figure 1).
Verification Compiler provides comprehensive support for all simulation flows, including native low power, X-Prop, planning, coverage and execution management. Verification Compiler also supports industry-leading debug flows, including power-aware and HW/SW debug. It also provides access to Synopsys' next-generation static and formal technologies, with advanced low power static checking, formal verification, Clock Domain Crossing (CDC) checking and advanced lint. Verification Compiler makes all of Synopsys' next-generation VIP titles available in simulation and debug flows (See figure 5).
Verification Compiler offers compelling integration features, providing up to 5X performance improvements, 3X productivity improvements, and greatly increased debug efficiency. Finally, Verification Compiler provides users uniquely flexible access to simulation, static/formal and debug features to enable concurrent verification. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2014-3-28 23:50:02
