Cadence BJ 招聘Principal/Lead Design Engineer (数字前端设计)

kengteng

Title: Principal/Lead Design Engineer (数字前端设计)

Job location: Beijing

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

Ifyou have interest, PLS send your update CV to zhangyl@cadence.com

Position Description:

Deliver/implementDDR IP. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

- Beresponsible for building and leading a high-performance IC design team, owningthe IC micro-architecture, package and test platform development, refining theEDA design flow

-Proficiency in logic design, simulation, synthesis, STA and testing

-Proficiency in Verilog and its simulation environment

- Goodknowledge of IC design

* At leastfive years experience driving complex IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment.

  

Position Requirements:

1. EssentialQualifications: Must have BS degree with 8+ years of applicable experience, MSdegree with 5+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.

2. Essentialthat the individual demonstrates strong communication, verbal and written. 3. Requiresgood communication skills in English.