Cadence BJ 招聘Principle Verification Engineer (前端验证)

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Cadence BJ 招聘Principle VerificationEngineer (前端验证)

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Position Description:

Deliver/implement advanced verificationsolutions by utilizing Cadence’s Incisive Verification product portfolio. Theengineer should be able to act as a strong team member and contributor, leadingteam projects and initiatives. Exercise judgment within generally definedpractices and policies.

Specificduties include:

--Deep understanding on ASIC/SOC design flow

--Excellent knowledge of advanced verificationmethodology like eRM/OVM/UVM

–Familiar with Cadence’sIncisive Plan to Closure Methodology (IPCM)

--Proficiency in System Verilog, System Cand/or e (Specman)

–Developing and usingVerification Components (eVC,OVC,UVC,VIP)

–Developing and usingassertion based verification and formal analysis methods

--Skilled in scripting language,such as Perl,Cshell,Python,Makefile

–Assessing the projectverification requirements

–Operating in a lead roleregarding architecting and implementation of project verificationenvironment/solution.

–May coordinate/lead otherswithin the scope of a defined project

Position Requirements:

EssentialQualifications:

- BS degree with 8+ years of applicableexperience,MS degree with 6+ years of applicable experience in electricalengineering,microelectronics,comparable engineering science or solid statephysics.

- Essential that the individual demonstratesstrong communication,verbal and written. Requires good communication skills inEnglish.

DesirableQualifications:

- A minimum of four years relevant experiencein industry.

- Will have demonstrated hands-on experienceand expertise with Cadence verification design tools or equivalent tools, flowsand methodologies required to execute a verification project.

- Will have demonstrated successful completionof 6+ verification projects as an individual contributor

- Will have DDR project verification experience