Cadence BJ 招聘Principle Verification Engineer (前端验证)

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Cadence BJ 招聘Principle Verification Engineer (前端验证)

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If you have interest, PLS send your update CV to zhangyl@cadence.com

Position Description:

Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:

--Deep understanding on ASIC/SOC design flow

--Excellent knowledge of advanced verification methodology like eRM/OVM/UVM

–Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)

--Proficiency in System Verilog, System C and/or e (Specman)

–Developing and using Verification Components (eVC,OVC,UVC,VIP)

–Developing and using assertion based verification and formal analysis methods

--Skilled in scripting language,such as Perl,C shell,Python,Makefile

–Assessing the project verification requirements

–Operating in a lead role regarding architecting and implementation of project verification environment/solution.

–May coordinate/lead others within the scope of a defined project

Position Requirements:

Essential Qualifications:

- BS degree with 5+ years of applicable experience,MS degree with 4+ years of applicable experience in electrical engineering,microelectronics,comparable engineering science or solid state physics.

- Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English.

Desirable Qualifications:

- A minimum of four years relevant experience in industry.

- Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.

- Will have demonstrated successful completion of 6+ verification projects as an individual contributor

- Will have DDR project verification experience