后端-backend engineer

bestgrace

后端-backend engineer 简历发bestgrace@qq.com

Job Description:
        Responsible for physical design implementation of complex SoCs (Netlist-to-GDSII). Work on block level or SoC level physical design in 28nm/20nm technology.
        Floorplan, placement, routing, clock tree synthesis, timing closure, signal integrity fixing, DRC/LVS.

Requirements:
- BS, MS, PhD, in computer engineering or electrical engineering
-MUST have at least 2 years of experience in physical design
-Must have successfully taped out at least one complex chip
-Hands on experience with tools like ICC (Synopsys), SocEncounter (Cadence) or Talus (Magma)
-Working knowledge of STA(Primetime), power analysis, DRC/LVS a plus
-Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
-Working knowledge of RTL-to-Netlist such as synthesis, DFT is a plus but not a requirement
-Programming experience in Perl/Tcl a big plus

Grace Li
@ Hi-Talent Consulting Co. , Ltd.

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E-Mail:bestgrace@qq.com

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