NO.277-ASIC Digital Verification Engineer（Shanghai）

kthr

Responsibilities:
  Make verification plan for one module or whole chip.
  Build up and maintain module-level and chip-level verification environment
  Verify ASIC digital design based on case list, and output verification report.
  Also responsible for lint checking and formal verification.

Qualifications:
  Proficiency in logic verification.
  Experience with Verilog logic design language.
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.
  Experience with UNIX/Linux simulation tools such as IUS or VCS.
  Experience with C and C++ is a plus.
  Experience with C_SHELL, TCL or PERL is a plus.
  Experience with UVM, OVM or VMM is a plus.
  Good knowledge of SOC design is a plus.
  Good knowledge of software design is a plus.
  Self-motivated and good team player.
  MSEE or BSEE with 2+ years.

KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.

If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!
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