Senior verification Engineer

bestgrace

Senior verification Engineer  



Job description:



1.Understanding the expected functionality of designs.

2.Developing testing and regression plans.

3.Designing and developing verification environment including co-verification.

4.Running RTL and gate-level simulations.

5.Code/functional coverage developments, analysis and closure.



Requirement:

1.A MSEE with minimum of 3 years experience or a BSEE with a minimum of 5 years experience in digital circuit design.

2.Design verification experience(test plan, test bench, assertions, debugging designs,code overage ect.)

3.Knowledge in ASIC/FPGA design process and verification tools.

4.Familiar with design and verification languages (Verilog, System Verilog, SVA etc)

5.Scripting and automation skills (tcl, perl, makefile ect) a plus.

6.Independent and self-managing.

7.Good communication skills and team work experience.







Grace @ Hi-Talent Consulting Co. , Ltd.

上海芯得企业管理咨询有限公司

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