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Title: Senior Backend Engineer
Perform physical design implementation, including synthesis, floor planning, power grid
design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff,
physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design
project management.
-The candidate will have the opportunity to work on many varieties of challenging designs,
i.e. low power and high speed design. The responsibility includes participating in or leading
next generation physical design, methodology and flow development.
Position Requirements:
1. BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable
experience in electrical engineering, microelectronics.
2. Experienced with ASIC design flow, hierarchical physical design strategies, and
methodologies and understand deep sub-micron technology issues.
3. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk
analysis, formal verification, physical verification, DFM.
4. Successful track records of taping out complex, 65/40/28 nm SOC chips.
5. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
6. Self-motivated, able to work independently or as a team player, excellent verbal and
written communication skills in English.
Grace @ Hi-Talent Consulting Co. , Ltd.
上海芯得企业管理咨询有限公司
E-Mail: bestgrace@qq.com
QQ: 2043753191
新浪blog:
http://blog.sina.com.cn/u/1767088102
新浪微博:
http://weibo.com/bestgrace
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