【全职】AMD 招聘多个岗位技术工程师

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1.Job Description

Position Title		Design Verification MTS for Graphics Hardware
Organization	SRDC, GC		Function	R&D
Location	Shanghai		Rep/Add	Add.

Position Summary

In this key role, the candidate will be responsible for low powerimplementation and verification of hardware.

Key Relationships

Report To:                    Manager of SRDC

Direct Reports:              0

Essential Functions:

• Development of infrastructure for verification of hardware in     GFX IP.
• Develop verification environments for feature verification,     and use the automated regression infrastructure setup for IP level and IP     on SoC level functional verification.
• Low power design and verification for specific hardware     functionality in Front-end.
• Improve the low power IP delivery for variant SoCs

Requirements/Qualifications:

• BS, MS or PhD in Electrical Engineering or Computer Science.
• 6+ years of ASIC verification or low power design experience
• Should have good understanding of Pre-Silicon design process     from Architecture, Design, Synthesis and Gate level Implementation till     Tapeout release.
• Advanced programming knowledge on Verilog/SystemVerilog, C/C++
• Requires demonstrated technical expertise in the areas of Design     Verification and low power design/verification methodology.
• Knowledge on Perforce, OVL, SVA, SV, UVM, script programming     etc.
• Should have excellent communication skills (both written and     oral) and should be able to participate cross functional engineering teams     geographically.
• Demonstrates leadership ability preferred.

Skills/Competencies:

·
Good design verification experience

·
Good communication

·
Strong problem solving skills

·
Low power design verification or computergraphics knowledge are plus

Desired:

·
Team Lead experience

·
Design Verification experience

2.Member of technical staff for IC designverification (MTS DV)

Requirements:

Thecandidate is preferred to be MSEEwith minimum of 6 years, or BSEEwith minimum of 8 years experience indigital ASIC/SOC design verification.  

Thecandidate must have:

1.
deep understanding on ASIC/SOC design flow

2.
Excellent knowledge ofdesign verification methodology, such as VMM or OVM and UVM.

3.
Solid experiences with simulation model creation and the testbenchbuild

4.
Strong RTL coding with Verilog

5.
Strong SystemVerilog experiences.

6.
Strong C/C++ software development experiences

7.
Be good at scripting language, such as Perl, Cshell, Ruby, and Makefile.

It is a must that the candidate has one or more of thefollowing experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB)bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCIbus, low power design, clock generation and control, SD/eMMC host controller,SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), Ethernet, JTAG, etc.

Thecandidate is expected to exhibit good verbal and written communication skillsin both Chinese and English, specialized knowledge plus broad technicalknowledge that facilitates integrative thinking, , driving execution of qualityand timely result, capability  to solvecomplex, novel and no-recurring problems and decision-making on criticaltechnical areas

Hands-onlab experience is another plus, able to understand and/or use the use scopes,logic analyzers, has knowledge or skill of board-level lab debugging.

Responsibility:

Thesuccessful candidate will work with team members and apply current functionalverification techniques to perform and improve pre-silicon verification qualityand product Time to Market for Southbridge design. The candidate will providethe technical leadership to the DV team for the new Southbridge project. He/Sheshould be able to work independently on various DV tasks and providingtechnical guidance to the DV team. The candidate would involve technically inthe porting/creation of the DV environment for the new design, block and chiplevel test plan creation and implementation, coverage analysis, and regressioncleanup.

3. Software Engineering

Area of Interest:	Software  Engineering
Job Title:	FCH Driver/OS Architect(PMTS)
Location	Sunnyvale or Shanghai
Country:	US or China
Job Description:          DESCRIPTION OF DUTIES:    - Architect, design and guide the implementation of  all Windows and Linux software- ranging from kernel, middleware to application    - Understanding current and planned hardware  functionality and be able to define software directions aligned with silicon  features    - Distill  industry and technology trends into actionable software (and hardware)  deliverables    - Working with  senior architects and fellows across AMD to ensure that our technical  directions are aligned with other areas of the corporation    - Working with management team to understand,  clarify, and shape requirements, and to translate these into technical  requirements used to design the product   - Regular communication via  Audio/Video conference with Global Teams          PREFERRED EXPERIENCE:    - MS-EE/MS-CS  with at least 10 years’ experience in Windows/Linux system development, or 7 years’  experience for PHD degree    - Excellent and  demonstrable C/C++ programming skills    - Deep understanding of x86 architecture    - Strong kernel, device driver development  experience, Linux kernel  or Windows device driver experience is a plus    - Deep understanding on at least  one controller in South Bridge (SATA, USB, etc) or power management under X86  architecture    - Strong analysis  and problem solving skills required    - Experienced project planning and prior technical  leadership responsibilities    - Proven interpersonal skill, technical  leadership and teamwork required    - Must be fluent  in both written and spoken English    - Experience  working with multi-site teams preferred

4.JD: MTS/SE for Camera/ISP SW Development (Windows)

PREFERREDEXPERIENCE:

-BS-CS/BS-EE with at least 7 years’ experience in Windows device driverdevelopment, or 5+ years’ experience for MS

- Good at C/C++ language, demonstrable C/C++ programming skills

- Experience with Windows AVStream Framework or Multimedia driver

- Solidunderstanding of Windows Driver Architecture (WDM/WDF)

-Experience with ISP, camera sensor tuning activity.

- Goodunderstanding of embedded system and/or tablet architecture is a plus

- Knowledgein ISP(Image Signal Processing), video encoding/decoding is a plus

-Strong analysis and problem solving skills required

-Proven interpersonal skill, technical leadership and teamwork required

-Fluent in both written and spoken English
- Experience of working with multi-site teams preferred

KEYResponsibilities:

-Architect, design and implement Windows Camera/ISP solutions for AMD PlatformSolutions

-Closely interact with ASIC design team in new feature definition and bring upfor future product generation

-Improve customer satisfaction and product quality by solving technical problems

-Accountable on time delivery of deliverables

-Collaborate and interface with local and global management, development andtest teams to deliver a complete product solution

-Regular communication via Audio/Video conference with global teams

5.Job Description

Position Title		Sr.  Fro-end ASIC Design CAD engineer
Organization	Technology and Engineering		Function	CAD
Location	Shanghai		Rep/Add	Rep

Position Summary

l
Participatein the design and implementation of the leading edge, front-end ASIC designflow

l
Participatein the research of Design Methodology to improve automation and  productivity to produce AMD's newhigh-quality cutting-edge APU and GPU products

l
Technicalsupport and programming

l
Interfacewith EDA vendors on technology

Key Relationships

Reports To: AngelaXue

Direct Reports: AngelaXue

            

Peer Relationships:      

Other Relationships:      

                                                        

Essential Functions:

Essential Requirements/Qualifications:

1.
Major in EE, CS or related, Master Degree with 3+ years or Bachelorwith 5+ years working experience

2.
Experience in Front-end digital design and VerilogHDL is required

3.
Good programming skill with one or more languages (e.g. Tcl, Perl,python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow

4.
Familiar with SRAM design and behaviour is a plus

5.
Familiar with one or more ASIC flows (logic synthesis, STA etc.)and usage of related EDA tools is a plus

6.
Good written and spoken English

7.
Good communication skills and be able to work both independentlyand in a team

6.Position Summary

Job Title:	Senior Staff/Staff  Design Lead for Wired  Connection IP
City/Town:	Shanghai
Country:	China

- Participate IP and SoC level architecture definition, create IParchitectural spec, derive functional and design specifications and analyzefeasibility of technical and architectures.

- Implement design with Verilog to achieve specification goals. Simulateand debug the codes in coding stage.

- Define timing constraints and support the FE Integration team todeliver qualified netlist. Feedback to Physical Design team to help to closetiming and check floorplan

- Discuss with SW team to generate an optimized HW/SW partition of thefunctionalities

- Support FW/SW bring-up and debugging

- Working as the technical point of contact in the Wired Connection IParea.

- Maintain design environment, solve flow issues, and develop scripts toimprove flow efficiency.

                                                        

Essential Functions:

Architecture,RTL, Synthesis, STA, Timing Analysis, Constraints

Essential Requirements/Qualifications:

- Proven IP /SoC Design / Integration Experience

- Must have strong background on IP development

Desired:

- Enthusiasm ontechnical topics

- Major in EE& CS

- Must be proficient in Verilog coding, debugging and modeling

- Deepunderstanding of below technical aspects would be an asset:

·
10GbE+ solutionsfrom the industry leading companies

·
basic offloadengines used in 10GbE/40GbE, such as

o
TCP transmitsegmentation offloading

o
TCP Large receiveoffload

o
Receive sidescaling

·
Basic filteringand Classification: Unicast/multicast/broadcast, ACLs

·
Advancedfiltering and classification: flow based and L3 protocol based

·
Data-centerbridging, PFC/ETS/DCBX/QCN

·
Devicevirtualization, SR-IOV/VEB/VEPA

·
Advanced offloadengine

o
TCP offload: TOE

o
Storage offload:iSCSI HBA/FCoE HBA

o
RDMA: RoCE/iWARP

o
Security offload:IPSec

- 10 gigabit+ Ethernet IP design experience would be an asset

- Ethernet HW/SWperformance analysis experience would be an asset

- Be familiar with ASIC design flow, such assynthesis, DFT, timing analysis, ECO etc

- Be familiar with shell/perl/tcl programming in linux OS.

- Should have strong problem solving skills

- Good English hearing, speaking, reading and writing capabilities

- Good communication skills

- Have mass production tape‐out experience