猎头-IC验证/设计工程师，项目经理，软件工程师

bestgrace

Position located in Shanghai:
1. Customer Program Manager
RESPONSIBILITIES:
- Determine strategy and tactics for executing product solutions from business
/design award to production.
- Develop program schedules, milestones and deliverables.
- Translate customer requirements into specific tasks for all functional areas
and proactively capture, track and drive all issues to closure.
- Communicate issue status to the customer and internal teams.
- Correctly represent the urgency of issues and escalate issues appropriately.

- Work closely with the hardware and software engineering teams, operations, F
AEs and Sales teams to resolve technical and logistical issues.
- Regularly communicate the program status and key issues to management.
- Develop a close working relationship with the customers development team and
use creativity to find solutions to their issues.
- Develop and maintain pertinent metrics/KPIs for measuring program and proces
s health/effectiveness.

MINIMUM REQUIREMENTS:
- 5+ years in PC or related industry
- Proven history of Project/Program Management of software and hardware produc
ts
- Strong technical background and experience working with customers in an OEM
environment
- Experience managing global projects
- Excellent verbal and written communication skills (English and Mandarin)
- BS/MS Engineering or Computer Science preferred

2. SOFTWARE QA ENGINEER

Job Description/Qualifications:
- Develop automation test tool
- System chipset drivers testing to ensure functionality and compatibility
- Maintain and execute driver test plans on a daily basis
- Set up and maintain test system infrastructures

MINIMUM REQUIRMENTS:
- The candidate should be experienced C/C++, C# is perfect
- 2+ years of platform driver/System BIOS experience
- Good knowledge of PC Chipset and core logic technologies a plus
- Good trouble shooting and analytical skills a plus

3. PHYSICAL DESIGN ENGINEER

RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphic
s processors, integrated chipsets and other ASICs targeted at the desktop, lap
top, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodo
logies, flow automation, chip floorplan, power/clock distribution, chip assemb
ly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end ver
ification across multiple projects

MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 2+ years of experience in large VLSI physical design implementation on 0.15u
, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drive
rs
- Prior experience in Timing closure, clock/power Distribution and analysis, R
C Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power
and timing
- Circuit level comprehension of time critical paths, and spice experience a p
lus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (A
stro/PC/dc_shell/pt_shell/STAR-RC), CADence (FE/Nanoroute), Sequence (Physical
Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred

4. GPU-ASIC-Physical Design Engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining the
chip infrastructure process across product designs, focusing on such tasks as
clocks/timing/convergence/design for test and scripting of flows. You’ll be f
ocusing on full chip layout planning (partitioning, planning clock distributio
n and other structure, methodology), partition/full chip timing closure (prime
time scripts, other tools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:
- Work in conjunction with Place and Route Engineers to achieve timing closure
for both partition level and full chip level
- Develop and enhance entire timing flow from Frontend (pre-layout) to backend
(post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, s
pecial circuits such as clock dividers, core logic <-> IO macros interfaces su
ch as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.

MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in tim
ing
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environ
ment
- Keep up to date with leading edge technologies

5. ASIC Verification Engineer

RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Develop and execute verification plan
- Develop BFM
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation

MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC veri
fication
- Possess knowledge in at least one of the below areas
&#8226; HDCP/TMDS/LVDS/DisplayPort
&#8226; Blending, color space conversion
&#8226; Image up and down sampling
- Strong problem solving and analytical skills
- Must be proficient in Verilog HDL
- Must be strong in Perl programming, or strong in Python/Ruby programming
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus

6. ASIC DFT VERIFICATION Engineer

Responsibilities:
- Develop and maintain DFT verification environment at full chip
- Develop test DFT cases and procedure
- Responsible for running both RTL & gate level simulation
-Generate test vectors and post silicon validation

Requirements:
- BSEE required, MSEE preferred.
- 2+ years of experience in DFT/design field
-Strong logic Design and verification back ground
- Possess strong Knowledge of DFT (scan insertion, MBIST, JTAG and etc.)
- Proficient in logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Proficient in Verilog HDL
- Strong in Perl/tcl, programming
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus
- Strong problem solving and analytical skills

7. Infrastructure Architect

RESPONSIBILITIES:
- Develop the core infrastructure for modeling, analysis, verification and deb
ugging in the development of large scale graphics chips.
- Develop/maintain the proprietary internal tools for the building process on
various functional and performance simulations of future chips.
- Work closely with worldwide project members and users to specify system, cre
ate schedules and manage ongoing feedback and enhancement releases.

REQUIREMENTS:
- Bachelor’s degree in CS, EE or related majors. Solid system level knowledge
.
- Strong C/C++ programming ability, proficient makefile development skills.
- Strong scripting language (Perl preferred) programming ability, well versed
in developing/debugging on Linux/Unix.
- Minimum 2 years experience in one of the areas:
&#8226; EDA CAD.
&#8226; Software integration/testing/incremental building/version control.
&#8226; Large scale scripting system development.
- Familiar with one version control tool, perforce preferred.
- Experience on Linux cluster is a plus.
- Experience on Cygwin is a plus.
- Well organized problem solving capability and communication skills.
- Proactive, creative and a team player.
- Excellent English writing/speaking skills.
8. Graphics/Compute Architect

RESPONSIBILITIES:
- Design and develop state of the art GPU hardware, in the area of graphics mo
dules, computation units, data communication units, or memory controllers
- Working within a team of graphics architects and ASIC engineers to document,
design, develop and verify functional and performance models for NVIDIA’s ne
w chips.
- Develop tests, testplans, and testing infrastructure to validate the perform
ance and functional correctness of ASICs modeled in C++, RTL and real silicon.

- Develop tests and tools to collect useful information for 3D graphics perfor
mance analysis.

REQUIREMENTS:
- Bachelors degree in CS, EE, or Math. Advanced degrees are helpful.
- Minimum 2 years experience in one of the areas:
Microprocessor architecture design & development
3D graphics drivers (d3d or OpenGL) development
System level programming experience in OS, Compiler, software tools, virtual m
emory system
Parallel computing/HPC related development
- Strong CS background with OS, Compiler, Debugger and system level programmin
g and debugging skills
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) ex
perience is a plus, CUDA experience is another plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Familiar with 3D graphics APIs, d3d or/and OpenGL is a plus
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well e
nough to attend meetings

9. ASIC Design Engineer

RESPONSIBILITIES:
- ASIC Design for display subsystem
- Micro-architecture definition; working closely with video/graphics/system ar
chitects.
- RTL design, verification, synthesis, timing, and silicon bring-up.

MINIMUM REQUIREMENTS:
- 3+ years experience in logic design/verification.
- Must be familiar with standard industrial tools like VCS/DC/Verdi/NCsim and
etc.
- Knowledgeable in designing image post processing system (color space convers
ion, up/down scaling, sharpening, de-interlacing and etc.)
- Knowledgeable in standard display interfaces like HDMI/LVDS/DisplayPort is a
plus.
- SystemVerilog experience is a plus.
- Programming skills in C and PERL preferred.
- Good communication skills and proven ability to work well within a team.
- BS in Electrical Engineering, MS preferred.

10. OpenGL Performance Tools Software Engineer

The 3D Performance Tools Software Engineer will have the primary responsibilit
y to design and implement 3D graphics profiling and debugging applications for
the PC, Embedded and Mobile 3D development community. The successful candidat
e will develop applications that will assist developers with identifying bottl
enecks and inconsistencies in their 3D graphics application by exposing Driver
and Hardware Performance Counters, and presenting the information in a way ca
n be understood by external developers. By listening to the needs coming from
the 3D graphics community, the engineer will provide professional solutions to
level out the difficulties arising from the development of high-end 3D graphi
cs application.

- 5+ years of experience in programming. 2+ years master, or 5+ years bachelor
- Strong object oriented programming and methodologies.
- In depth knowledge of at least one 3D graphics API: OpenGL, OpenGL ES or Dir
ect3D.
- Strong mathematic skills.
- C/C++
- Experience in 3D Driver Development is a big plus

11. Embedded Software Engineer
Job Description/Qualifications:
- Good English language skills to work effectively with global development and
support team
- Excellent C skills
- Excellent debugging and problem solving skills
- Experience working on embedded systems and ARM processor specific;
- Prior experience in Linux software development is a plus;
- Self managing and ability to break down complex problems in to manageable ta
sks;
- Enjoys working with customer from design to production

12. CUDA DevTech Engineer

Job Description/Qualifications:
NVIDIA is searching for world-class software engineers for an exciting role in
Developer Technology. Work with the most exciting high-performance computing
applications, on cutting-edge computational systems, with developers throughou
t the world. Interact closely with the architecture and software teams at NVID
IA to ensure the best possible performance and results. Work to help influence
the developer experience with current-generation hardware as well as determin
e trends and features for next-generation architectures. You will work with th
e latest GPU technology working with HPC, Visual Consumer, and Professional ap
plications.

For HPC and Professional Applications, you will work on parallelizing software
algorithms for applications in a variety of fields including geo-sciences, me
dicine, computational biology, and digital content creation tools.

For Visual Consumer applications, you will work with video, photo imaging, com
puter vision consumer applications.

An important part of this role will be to support, evangelize, and influence N
VIDIA GPU in either graphics or general purpose computing technologies to deve
lopers. You will develop and implement new data-parallel algorithms and system
s, create technical demos, write whitepapers and present your work at conferen
ces. Through collaboration with external software developers, you will help to
optimize their products using NVIDIA technology.

MINIMUM REQUIREMENTS:
Skills Required:
- Strong knowledge of C/C++ and programming techniques
- Strong mathematical fundamentals, including linear algebra and numerical met
hods.
- Good communication skills required.
- Travel for on-site visits with developers and to conferences will be require
d.
- Ideal candidates will have experience with parallel programming, especially
data-parallel and/or GPGPU.
- Minimum 3 years of industry or aCADemic experience (or equivalent) in a rela
ted field.
- B.S. or higher degree in Computer Science/Engineering or mathematical field.
- Experience with OpenMP, MPI, Fortran, and parallel programming is a plus
- Experience with CUDA, DirectX, or OpenGL is a plus.
- Experience in benchmarking a plus
- Familiar with CPU System architecture and OS fundamentals.
- A strong team player that is self motivated.

E-Mail: bestgrace@qq.com
QQ: 2043753191
新浪blog: http://blog.sina.com.cn/u/1767088102