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Principal/Lead Physical Design Engineer (5 Positions)
[url=mailto:%E7%AE%80%E5%8E%86%E5%8F%91bestgrace@qq.com]简历发bestgrace@qq.com[/url]
联系QQ: 2043753191
Position Description:
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Perform physicaldesign implementation, including floor planning, power grid design, place androute, clock tree synthesis, timing closure, power/signal integrity signoff,physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
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The candidate will have the opportunityto work on many varieties of challenging designs, i.e. low power and high speeddesign. The responsibility includes participating in or leading next generationphysical design, methodology and flow development.
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Ability to handle large sized designimplementation tasks alone
PositionRequirements:
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BS degree with6~10+ years of applicable experience, MS degree with 4~7+ years of applicableexperience in electrical engineering, microelectronics.
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Experienced withASIC design flow, hierarchical physical design strategies, and methodologiesand understand deep sub-micron technology issues. Solid knowledge on LP Design,DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formalverification, physical verification, DFM. Successful track records of tapingout complex, 65/40/28 nm SOC chips.
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Automation andprogramming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
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Self-motivated,able to work independently or as a team player
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Excellent verbal and writtencommunication skills in English.
E-Mail: bestgrace@qq.com
QQ: 2043753191 新浪blog: http://blog.sina.com.cn/u/1767088102
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