MCU design和verification

jj_seu

MCU design and verification engineer

CPU Verification

QQ: 983144394

Email: jj_seu@hi-talent.net

#1 Senior system design engineer

Job description:

The candidate will be responsible for:

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Design and integration an AXI/AHB based system including host processor, DDR controller, SD/MMC, Display I/F and other peripherals., as a verification/demo platform for the in-house designed video IP’s;

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Build up the simulation based environment for the system, for the functional verification;

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Investigate and develop related drivers for the used IP’s in the system;

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Use ISE/Vivado/Quart, implement the design to Altera/Xilinx FPGAs,

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Work with SW engineer, to bring up system/OS on the FPGA prototyping board. Debug and resolve failures with Logic Analyzer and/or ChipScope/SignalTap;

Qualification:

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BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;

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Must be highly self-motivator and good team player;

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Good understanding and hands-on experiences in SOC development and related methodology;

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Solid skills in logic design with Verilog/VHDL, timing closure and analysis;

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Familiar with FPGA implementation with ISE/Quartus and debugging;

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Knowledge and hands-on experiences in at least 2 of the below fields are required;

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AXI/AHB bus protocols;

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Design or bring-up of DDR2/3 controller/PHY;

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Display interfaces/protocols such as LVDS/HDMI;

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SD/MMC controller;

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NAND/NOR flush controller；

#2. CPU Verification Intern

Job description:

The candidate will take part in verification for the in-house designed CPU/MCU, including:

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Maintain and improve the verification environment and flow;

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Make the test plan according to the design specification, and execute it with System verilog based coverage monitors/assertions;

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Develop direct tests and constraint random tests;

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Coverage data collection and analysis;

Qualification:

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Graduate student who will graduate in 2015, major in electronic engineering/micro-electronics;

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Must be highly self-motivated, eager to learn and accept new knowledge, a quick learner;

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Could work at least 4 days every week;

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Knowledge and understanding of computer architecture and micro-architecture of RISC processors

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Familiar with front-end ASIC design flow and Verilog HDL;

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Familiar or experiences in high-level verification methodology (VMM/UVM/OVM), and/or hardware verification language (SystemC/SystemVerilog) would be a great plus;

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Experiences or skills in assembly programming, and using scripting languages (Perl/Tcl/Shell) for flow automation is a plus;

#3. (Senior) MCU design and verification engineer

Job description:

The candidate will be responsible for in-house micro-controller design and verfication, including:

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Micro-architecture definition;

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Logic implementation with Verilog HDL;

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Functional verification and performance tuning;

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Synthesis and timing closure;

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Develop direct tests and constraint random tests;

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Coverage data collection and analysis;

Qualification:

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BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;

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Must be highly self-motivator and good team player;

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Solid skills and rich experiences in logic design, synthesis and timing analysis;

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Familiar with all front-end flows including LINT check, simulation, synthesis, STA, formal and power analysis, etc.;

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Knowledge and experiences in Computer Architecture and RISC processor (ARM/MIPS/SPARC) micro-architecture, familiar with associated tool-chains such as compiler, assembler, debugger etc.;

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Familiar with CABAC algorithm in video coding standard such like H.264/AVC and HEVC or hands-on engineering experiences in video codec development is a big plus;

ICSYS

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