[猎头](Sr.) ASIC Design Verification Engineer

bestgrace

职位描述:

Position description:

Run simulation for module and chip level (mainly in SerDes IP/Chip), work closely with designer;

Develop and execute verification plan;

Define, implement and analysis functional/code coverage;

Develop/maintain/enhance environment (TB/tools/scripts/flow).



Requirement:

Proficient and experienced in one of the high level verification methodology (VMM, UVM);

Experienced with hardware verification language (Vera, SystemC, SystemVerilog)

Proficient with Verilog HDL;

Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl

Familiar with ASIC design flow

Master degree in EE

Experienced in SerDes PHY(USB3, SATA, SAS, PCIE etc) is a plus.





E-Mail: bestgrace@qq.com

QQ: 2043753191

新浪blog:
http://blog.sina.com.cn/u/1767088102

luyuan_0922

any job located in Xi'an????