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本帖最后由 Storage_Network 于 2013-7-28 18:04 编辑
最近长三角像是着了火一样，天天高温，前天上海徐家汇更是达到了40.6度。虽然天气让人体感不适，
但LSI对高端IC人才的渴求像极了现在的天气，火一样地欢迎您。
最近LSI又有16个职位开出，涵盖各个方面，虚位以待各路高人大牛的加入。
LSI现在位于徐汇区高品质写字楼徐汇苑大厦内，耸立在美丽的八万人体育馆旁边，拥有方便的轨交一号线四号线。
年底LSI会搬迁到浦东的国家级科技园张江，在那里，LSI拥有独栋的研发大厦，里面有完善的各种设施，办公，娱乐，
生活都非常方便。为了员工通勤便利，LSI还准备了班车，覆盖上海主要地区。最近两三年内，
LSI员工的规模会增长50%（现在500+人）到750人，LSI上海将成为全球三大研发中心之一。
LSI给员工提供业界有竞争力的薪水和福利，同时LSI在对待招聘方面一直非常严肃并且声誉良好，一口唾沫一口钉，
只要发了offer,从来没有反悔过的情况。
如果您感兴趣下面的职位，简历请寄送至Storage_Network@hotmail.com,期盼你的垂询！职位介绍如下：
1.Product Engineering Manager --1 position
2.Test Engineer --4 positions
3.Test Operations Engineer --1 position
4.Product Engineer --2 positions
5.Digital/Mixed-Signal Verification Engineer--2 positions
6.Preamp Verification Engineer --2 positions
7.Read Channel Verification Engineer --1 position
8.ASIC Design Engineer --1 position
9.ASIC Customer Design Engineer --1 position
10.Senior Analog Design Engineer --1 position
1.Product Engineering Manager --1 position
Hand-on experienced leader to drive improved performance and execution across all LSI silicon products.
Willing to work with extended international teams across multiple time-zones and business units supporting product design,
marketing, sales, operations, quality and finance through interactions during product development and high volume
manufacturing. Good English skills are required.
A BS in EE is preferred with at least 5 years of hands on product engineering experience. A background in silicon wafer process
or test development is also a bonus. Must also have the ability to bring junior engineers up to speed in addition to having the
capability to independently make decisions at a high level. This role will work closely with test engineering, silicon design and
validation teams, program management – in addition to direct customer interfacing for China/APAC based customers.
Familiarity with standard product development cycle support needs and a laser focus on cost, quality and manufacturing
robustness is a big plus
Requirements/Qualifications (Education)
A BS in EE is preferred with at least 5 years of hands on product engineering experience. Good English skills a required. A
background in silicon wafer process or test development is also a bonus
2.Test Engineer --4 positions
- To support prototype and production releases of new products. Manage debug of test program, design and debug of test
hardware, and meet product release schedule
- Support test program development for implementing changes in new test methodologies for test coverage improvement
- Pursue Design for Test initiatives to optimize testability and achieve test cost reduction via test time reduction and multiple
site test solutions for production release
- Support test chip test development and characterization of new IP used in LSI products
Requirements/Qualifications (Education)
- University graduate students with top scores in GPA
- Prior working experiences in the semiconductor industry field, specially in either IDM, Fabless, or ATE vendor background
- ATE programming skills would be essential. T2000, U-flex platform knowledge is preferred
- VB, VC and/or Perl programming skills
3.Test Operations Engineer --1 position
- To support new product introduction into subcontractors and facilitate high volume ramp
- Manage execution deliverables covering test programs and all the essential test hardware and co-work with supply chain
management to meet/exceed on time deployment at subcontractors
- Drive KPIs at subcontractors to meet/exceed LSI performance metrics expectations
- Drive cost reduction and margin improvement initiatives to achieve the manufacturing cost objectives
- Support new technology/best practices evaluation/assessment, early adoption and introduction into subcontractors
- Ensure test process compliance to prevent manufacturing execursions
- Ensure compliance of quality requirements at subcontractors
Requirements/Qualifications (Education)
- University graduate (EE degree) with 5 years or more in product, test, and high volume manufacturing operations experiences
in the semiconductor area
- Solid background in high speed digital and mixed-signal testing is essential
- Working experiences with ATE andancillary test equipments. Teradyne Catalyst/UltraFlex, Advantest T2000, Delta/Seiko Epson
handlers and TEL/Accretech/Opus probers will be of advantage
- C++ and/or Perl programming skills
4.Product Engineer --2 positions
- Work as the owner of the product from Tape out to end of life.
- Support proto delivering, qualification, characterization before product is released to production.
- Responsible for product quality, including shipping quality level and reliability.
- Support customer issue.
- Drive cost saving, including yield improvement, test time reduction, 2nd source qual
Requirements/Qualifications (Education)
- BS or MS at Electronic Engineering area
- 3 years experience on IC industry, product engineering area
5.Digital/Mixed-Signal Verification Engineer--2 positions
A digital/mixed-signal verification engineer is required to implement critical top level UVM environments in a mixed-signal
context.
As part of the Mixed-Signal Verification Team, the successful candidate will:
- Drive mixed-signal verification of Storage preamp designs to ensure first pass silicon success, a critical role within the
Preamp organization.
- Work with the Preamp Mixed-Signal Design team to create mixed-signal testbench components, models, and simulation
environment.
- Create product test plans, test cases and perform simulation and debug of Storage preamp mixed-signal devices.
- Must be experienced with Verilog, SystemVerilog, and UVM. Specman-e and scripting languages is a definite plus.
- Ability to follow a disciplined verification methodology and work closely with a multi-location, international design team.
- Excellent teamwork and communication skills are required.
Requirements/Qualifications (Education)
- Preferred degree in Electrical or Electronic Engineering.
- BS required, MS or Ph.D. preferred
- The ideal candidate will have at least 5 years (BS) or 3 years (MS, Ph.D.) of experience as a member of a digital or mixed-
signal verification team.
- Experience with successful tapeout of SoC products from verification plan to sign-off including verification plan, reusable test
bench development, and regression
- Experience with UVM, Verilog, and SystemVerilog. Specman-e and scripting languages is a definite plus.
- Strong communication skills (must be proficient in both spoken and written English)
- Able to travel internationally (to United States and throughout Asia)
- Proven analytical skills and detail oriented
6.Preamp Verification Engineer --2 positions
LSI's Storage Peripherals Division is seeking an experienced verification design engineer to join the pre-amplifier design team.
Preamp design team members define, create, modify and verify high-speed custom integrated circuits for hard disk drive (HDD)
and tape recording products using leading edge CMOS and BiCMOS technologies
- Work with a Preamp Development team to create verilog testbench components and simulation environment.
- Create product test plans, test cases and perform simulation and debug of Storage Preamp mixed-signal devices.
- Must be experienced with Verilog and Verilog AMS and knowledgeable with functional coverage methodologies.
- Ability to follow a disciplined verification methodology and work closely with a multi-location, international design team.
- Excellent teamwork and communication skills are required.
Requirements/Qualifications (Education)
- Preferred degree in Electrical or Electronic Engineering.
- BS required, MS or Ph.D. preferred
- The ideal candidate will have 5 years of experience as a member of a Design Verification team
- Experience with successful tapeout of SoC products from verification plan to sign-off including verification plan, reusable test
bench development, random-constrained test case creation, RTL/Gate level simulation/debug, code/functional coverage
analysis and regression
- Conversant with Verilog, SystemVerilog, Specman, Perl/Python/Tcl scripts, Makefile and EDA tools
- Experience with Assertion or Formal Verification a plus
- Strong communication skills (must be proficient in both spoken and written English)
- Able to travel internationally (to United States and throughout Asia
- Understanding of silicon process technologies (CMOS and Bipolar) and device physics would be a plus.
- Conversant with Verilog-AMS/Verilog-A and Analog Behavior Modeling would be a plus
- Proven analytical skills (application of math and physics to solve problems
7.Read Channel Verification Engineer --1 position
As a member of the Read Channel team, candidate must be willing to work as an extended
member of the design team. Duties will include functional verification of Storage read
channel mixed-signal IP. Candidate will be expected to contribute to design and development
of System Verilog based verification environment and will be responsible for verification
closure of block/chip/system level functions for mixed signal based IP. Experience with
System Verilog and functional coverage methodologies are required. Must be willing to
follow a disciplined verification methodology and to work closely with a multi-location,
international design team. Excellent teamwork and communication skills are required.
PREFERRED EXPERIENCE:
BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.
Required knowledge and skills:
- Expertise in System Verilog required
- Good understanding of Digital Signal Processing
- Good understanding of Analog and Digital Circuits
- Very good analytical/debugging skill
- Good verbal and written communication skills
Desirable skills:
- Knowledge of Verilog-AMS, Perl
- Knowledge of verification methodologies including functional coverage and constrained
random testing
- Knowledge of VLSI design flows & DFT
- Familiarity of high level programming language
- Experience working with globally distributed team
8.ASIC Design Engineer --1 position
Candidate will be responsible for design and verification of functional blocks for Read Channel IC design team.
Responsible for front end block architecture /RTL coding and back end design activities including STA and
constraint generation
Requirements/Qualifications (Education)
BS/MS in Electrical/Computer Engineering |
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发表于 2013-7-28 17:51:10
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