【急招】---Sr. ASIC Engineer

jj_seu

mobile和high speed interface方面的asic 设计人才
Position: Sr. ASIC Engineer

1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.
2. IC/IP background. Be interesting in developing and improving New IP.
3. Integration experience, be able to own testchip tapeout.
4.  With at least 3-years IP/Product R&D experience.

Job Description
-       RTL coding, new logic design, simulation, synthesis.
-       Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.
-       Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.
-       Deliver design/verification/application documents.
Qualification and Experience
-     Very familiar with the Verilog HDL language;
-     Create the RTL architecture for the algorithm;
-     Very familiar with C and C++;
-     Familiar with FPGA tool, ModelSim, and Synplify.
-     Familiar with the flow of the IC design.

Requirements:
-    Bachelor/Master degree in electronic/computer engineering
-    Demonstrated abilities in working independently
-    Strong communication skills


欢迎把简历发给我，进一步电话沟通.
我一般上班时间不打电话，就是先发mail和短信飞信介绍一下基本情况。然后下班时候打电话的

1.       云计算工程师                                     上海或杭州
2.       数字前端 IC设计和验证                           上海
3.       数字后端 经理                                    上海
4.       射频 模拟 职位RFIC 和RF FAE    上海深圳

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Apple
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
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