Pixelworks(逐点)内部推荐急招

yaya126

美资公司，上海研发中心招聘 。

邮件请发送到celebraty2008@163.com， 谢谢。

Sr. Software Engineer

Job Description:

- MIPI and eDP SW driver development for low power chip

Requirements:

- Good experience in MIPI or eDP driver development in smart phone or tablet system

- Master or bachelor degree majoring in electronic engineering or computer science is preferred

- 2 years working experience for master degree or 5 years working experience for bachelor degree

- Strong C and/or C++ and/or ASM coding and debugging expertise

- Good experience in embedded system development

- Good Chinese and English communication skills

Job Description:

- MIPI and eDP SW driver development for display bridge chip

Requirements:

- Good experience in Linux or Android display driver development (not debugging or testing) in smart phone or tablet system with MIPI panels;

- or good experience in Windows or linux display driver development (not debugging or testing) in smart phone or tablet system with DP or eDP display;

- Master or bachelor degree majoring in electronic engineering or computer science is preferred

- 3 years working experience for master degree or 5 years working experience for bachelor degree

- Strong C and/or C++ and/or ASM coding and debugging expertise;

- nice to have experience Android application development experience;

- Good experience in embedded system development;

- Good Chinese and English communication skills;

Position: ASIC Engineer of SOC and Video system

Requirements

1.
BS or above in microelectronics, electrical engineering or equivalence

2.
3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.

3.
Must have one of following EDA tool experience

a)
STA, low power, DFT, synthesis

4.
Must have one of following design/coding experience, video related is preferred

a)
IP level micro-architecture definition, RTL design, co-work with verification owner

5.
Nice to have experience of chip level clock/reset structure definition, low power partition definition

6.
Good team work and communication skill (both in Chinese and English).

Responsibility

The candidate will be working on one of following items

1.
SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.

2.
Full chip timing closure, work closely with backend for tape out sign off

3.
Define UPF/CPF, verify low power structure base on RTL or NETLIST level

4.
Understand DFT/synthesis flow, provide necessary support

5.
Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner

Position: Sr. ASIC Engineer

1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.

2. IC/IP background. Be interesting in developing and improving New IP.

3. Integration experience, be able to own testchip tapeout.

4.
With at least 3-years IP/Product R&D experience.

Job Description

-
RTL coding, new logic design, simulation, synthesis.

-
Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.

-
Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.

-
Deliver design/verification/application documents.

Qualification and Experience

-
Very familiar with the Verilog HDL language;

-
Create the RTL architecture for the algorithm;

-
Very familiar with C and C++;

-
Familiar with FPGA tool, ModelSim, and Synplify.

-
Familiar with the flow of the IC design.

Requirements:

-
Bachelor/Master degree in electronic/computer engineering

-
Demonstrated abilities in working independently

-
Strong communication skills

yaya126

收到邮件已回复，简历周一推荐

hfsl

C:\modeltech_6.5\C:\modeltech_6.5\C:\modeltech_6.5\C:\modeltech_6.5\C:\modeltech_6.5\

jj_seu

我也有简历发HR@hi-talent.net

yaya126

人力外包公司请勿扰，这是公司内部推荐。