[全职]AMD上海多项职位招聘资深工程师

RecruiterAMD

AMD上海招聘资深工程师，请感兴趣的候选人务必以“所应聘职位_姓名_学历_专业_现公司
名称_工作年限” 为标题，
把简历以附件形式发送到maggie1.zhang@amd.com ,请在正文称述应聘理由与优势。

1.Title: MTS ASIC Design Verification Engineer – VIP DV
Req Number:  
Location: Shanghai/Beijing, China
Department: SCBU
Hiring Manager:
Recruiter:

AMD’s SCBU APU Design Verification team is looking for highly motivated Verif
ication Engineers to work on next generation APU SoC development.


KEY RESPONSIBILITIES:

-        Work closely with the SoC design team on understanding the APU system featur
es being designed;
-        Develop and execute test plans for system level functional features related
to Video Codec, Audio Processor, Display Port, Security, PCIe Controller;
-        Design, implement and improve verification testbench in Verilog, System-Veri
log, C/C++, OVM;
-        Develop and refine test libraries, model and test cases;
-        Apply functional coverage/assertion into testbench as enhancement;
-        Support bring-up test plan and silicon validation for video IP/solutions;


REQUIREMENTS:

-        At least 5 years DV experience with good understanding on IP level verificat
ion and system level verification;
-        Deep knowledge of Video coding standards such as AVC, MVC, SVC, HEVC, MPEG4-
2, VP8, MPEG-2, VC1 etc is a big plus;
-        Experience on Security, Memory Controller is preferred;
-        Experience with current verification methodologies (UVM, OVM, VMM...)
-        Experience using Perl or other UNIX scripting languages for flow automation
-        Good understanding on C/C++/Perl/Shell language;
-        Be fluent in English speaking and writing;

2.Position: MTS Design Engineer - DFT

Job Description:

Qualified candidate will perform some or all functions below:

1.        Participate in SOC full Chip DFT feature and architecture definition
2.        Responsible for DFT specification generation and review
3.        Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Mac
ro test logic.
4.        Perform verification on all DFT structures
5.        Generate DFT related timing constraints and work with PD team for timing cl
osure
6.        Generate and verify DFT structural patterns and functional patterns
7.        Participate in ATE bring-up and debug the DFT patterns on ATE
8.        Design and implement other DFX (debug, characterization, yield etc) logics
       

Requirements/Qualifications:


      -   BS in EE & CS.  MS preferred, with 4+ years experience.
-   Hands on working experience on ASIC DFT design and verification
-   Familiar with entire ASIC design flow
-   Experience with micro processor design a big plus
-   Should have strong problem solving skills
-   Good English hearing, speaking, reading and writing capabilities
-   Good communication skills

3.Senior /MTS Engineer of Physical Design
Job Description:        
Work with global Front-End design team and physical design team for large scal
e ASIC chip physical implementation. Focus on physical design of deep sub-micr
on GPU chips including block level (full chip) floor planning, timing closure,
place&route, physical verification etc. The individual is expected to be an e
xpert in multiple aspects in PD areas and provide technically leadership to th
e engineering team. The individual is also expected to be accountable for proj
ect delivery.
Job Requirement:
1.        MSEE with 6+ years or Bachelor with 8+ years of industrial experience in AS
IC design
2.        5+ years or more years of experience in physical design of deep submicron d
igital ASIC chips
3.        Hands on experience in large scale ASIC chip physical design
4.        Knowledgeable in all aspects of deep submicron ASIC design flow
5.        Successfully gone through several complete product development cycles
6.        Demonstrate strong leadership and work well with cross-functional teams
7.        Good listening, writing and speaking English
8.        Good communication skills, strong interpersonal skills and the flexibility
9.        Dedicated, hard working and good team player
10.        Familiar with Back-End (physical design) EDA tools
11.        Familiar with Front-End EDA tools is a plus
12.        Familiar with Unix/Linux environment and good at scripts


4.ISP tuning engineer

Location: Shanghai

[Responsibility]
1.        Image Sensor/sensor module calibration and tuning for AMD’s ISP;
2.        Image quality assessment, fine tuning, and certification for AMD and AMD’s
customers;
3.        Calibration/tuning tool chain development and process documentation;

[Requirement]
1.        Solid knowledge in optical system, imaging and image quality;
2.        Strong C/C++ and Matlab programming skills;
3.        Experience in mobile camera/sensor calibration/tuning process;
4.        Familiar with image and color processing techniques, include 3A(AWB, AE, an
d AF), gamma correction, demosaicing, denoising, WDR and etc.
5.        Familiar with image quality certification process is a plus;
6.        Master degree

5.ISP IP System Engineer

Location: Shanghai

[Responsibility]
1.        Support ISP Pre-silicon emulation
2.        Extract the feature list with design teams and from internal documents;
3.        Generate/maintain the detailed post silicon test plan for ISP IP enablement
and optimization by cooperating with the complete cross-functional teams;
4.        Generate the bring up plan with ISP bring up teams to collect, monitor and
track the bring up execution status updates.  
5.        ISP related issues debug/track/ close, including HW/SW issues, internal/cus
tomer issues;
6.        Cooperate with ISP validation to generate the validation test plan;

[Requirement]
1.        Experience with image sensor or products containing ISP;
2.        Solid knowledge in optical system, imaging and image quality;
3.        Good understanding of the chip design, implementation, and bring up process
es;
4.        Excellent communication and leadership skills among different functional te
ams;
5.        Experience in HW, SW, and system level debugging and triage;
6.        Familiar with semiconductor reliability;
7.        Experience in risk assessment and mitigation methodology.
8.        Fluent English both oral  and written;
9.        Master degree