[招聘]NVIDIA Physical Design engineer

gaoleeson

现有PD职位空缺，有意者可投简历（中英文）至邮箱lgao@nvidia.comJob Title: ASIC Physical Design engineerDepartment: GPULocation: ShanghaiJob Description/Qualifications:As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logicChip integration and netlist generationSynthesis, Formal verification, netlist quality checkWork in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip levelDevelop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.Develop flow to physically partition and floorplan the entire chip.Develop scripts for performing ECO's.Minimum Requirement:BS or MS in Electrical Engineering or Computer ScienceAbove 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closureExcellent scripts skillsExcellent written and verbal communication skills in EnglishAbility to multiplex many issues, set priorities, and work in a team environmentKeep up to date with leading edge technologies

pebay888

请问还再招吗？呵呵