NO.54-Digital Design Engineers for Mixed-Signal Power Management ASICs

KT人才

Location: Singapore

Responsibilities
Successful candidates will be responsible for leading, and participating in, the design and verification of leading edge ASICs in advanced digital CMOS processes for multi-function mobile platforms.

Skills/Experience
Design candidates will have a minimum of 2-3 years of relevant experience and must have detailed knowledge of digital ASIC design including architecture, RTL design for control and signal processing functions, linting, synthesis, STA, and DFT. Design candidates must also have experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence. Experience designing mixed signal interfaces and integrating digital modules into mixed-signal ASICs is desirable. Verification candidates should have a minimum of 2-3 years of relevant experience and must have detailed knowledge of self-checking testbench architectures (including directed and random-constrained generation) and coverage-driven verification techniques at the functional, assertion and code levels. Verification candidates will also have a working understanding of Object Oriented System Verilog principles. Experience with VMM, OVM, or UVM is desirable as is experience verifying digital modules in mixed-signal ASICs.

Education Requirements
Bachelor's degree in Electrical Engineering required. Master's degree in Electrical Engineering preferred.

KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!
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