Cadence SH 招聘 Principal PE and Principal Product Validation Engineer

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Cadence SH 招聘Principal PE and Principal Product Validation Engineer

If youhave interest, PLS send your update CV to zhangyl@cadence.com

1. Principal/Lead/Senior PVS Product Engineer

Position Description:

The Product Engineering teamworks with Customers and foundries, R&D, Marketing, and the FieldApplications Engineers to create products that address the unique and complexneeds of our customers. A Physical Verification Product Engineer providesin-depth technical expertise in writing Physical Verification rule decks (i.e.DRC, ERC, FILL and LVS) and the usage of Physical Verification tools throughoutphysical implementation and signoff verification cycles.

Responsibilities:

Develop Physical Verificationrule decks (i.e. DRC, ERC, FILL and LVS)

Setup efficient flows toimprove rule deck development quality and product performance.

Run expert-level benchmarksand solve complex customer problems.

Work with the RD, field,customers and foundries to identify and define product requirement and enhancement

Position Requirements:         

Knowledge of developing ruledecks for commercial physical verification tools (e.g. PVS, Calibre, Hercules,Dracula, Assura, etc.) is required.

Experience in the followingareas:

- DRC, includes density,antenna, etc.

- LVS, includes deviceextraction, parameter measurement, connect/stamp sequences, short isolation,etc.

- Knowledge of netlist formatsSPICE, CDL, Verilog, etc.

- DFM, includes yieldanalysis, via insertion, OPC, FILL, etc.

Experience with layoutimplementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.) for thecreation of qualification cells is required.

Knowledge of automating testsuites for the qualification of rule decks is a plus.

Programming of Tcl, Perl, andSkill are a plus

EDUCATION: BS or MS in ElectricalEngineering.

2. PrincipalProduct Engineer-----DDR IP

Position Description:

Cadence is lookingfor an individual to work in design IP team. The group provides configurableDDR memory controller and PHY IP for ASICs. The job will be mainly focused onproviding post technical support to customers; however there will be a varietyof other engineering tasks that will allow the candidate to expand skills andresponsibilities.

Providetechnical support to customers for integration of IP into ASICs including:

- Debugging ofcustomers’ simulation or silicon issues.

- Reviewing ofcustomers’ design integration of our IPs.

- Reviewing statictiming reports to assist with customers’ timing closure.

- Answeringtechnical questions about IP operation.

- Train fieldengineers in IP operation.

- Interface with theR&D Team to bridge product improvements and resolve customer issues.

PositionRequirements:         

- Excellent oral andwritten communication

- Good English communication skill

- BS  8+ yearsof prior work-experience or MS 6+ years of prior work-experience

- All front-endskills – RTL design & verification in Verilog, synthesis, static-timinganalysis, DFT

- Back-end skills –place & route, physical verification, timing closure

- Time managementskills sufficient to balance multiple high-priority projects.

- Willingness tolearn new skills and perform tasks that often go outside area of currentexpertise.

Additional Desirable Qualifications:

- Experience withStatic Timing scripts and report analysis

- Familiarity withDDR memory operation, system applications, AXI, OCP, AHB

- Familiarity withFrame maker

- Scripting – inPerl, TCL, etc..

3. Principal Product Engineer (Location:SH)

Position Description:  

1.Thisemployee will work in shanghai Engagement PE team, mainly focus on TSMC-relatedproject.

2.20nm and16nm FinFET flow establishment, from synthesis to final SI timing closure

3.Workclosely with other team members for technique communication and projects. Cantake lead role in project plan and action.

4.Co-workclosely with R&D team to find the debug the software problem in a ICbackend way as early as possible.

Position Requirements:         

1.Masterwith 7-8 years working experience or Bachelor with about 10years experience.

2.IC designbackground, especially in the back-end flow. Low Power related workingexperience will be a strong plus.

3.Syntheis,Backend experience, LVS, DRC, CLP knowledge and tape-out experience.

4.UnixSystem knowledge, vi/TCL/TK/CSH will be plus.

5.Strong scriptingcapability, including shell/tcl/perl.

6.Goodcommunication in English and Chinese, good confidence and good self-motivation.

7.Good teamspirit, well-aligned with the "One Cadence, One Team."

crazyhjh1314

还没招到，貌似有一段时间了啊